Skyworks Solutions Inc. CY28346ZC

Overview

CY28346ZC from Silicon Labs is a 3.3V clock synthesizer compliant with Intel® CK408 Mobile Clock Synthesizer specifications, delivering three differential CPU clocks (66–200 MHz), ten PCI clocks, five/six 3.3V 66 MHz clocks, and dual 48 MHz USB/DOT outputs. It integrates SMBus programmability, spread-spectrum EMI reduction, Dial-a-Frequency™ and Dial-a-dB™ features for dynamic frequency/current tuning in mobile platform timing subsystems.

For engineers reviewing the CY28346ZC datasheet, CY28346ZC pinout, CY28346ZC application, or CY28346ZC equivalent, this page provides verified technical context, validated pin functions, confirmed AC/DC timing parameters, and real-world implementation guidance for Intel mobile chipset reference designs requiring multi-domain clock distribution with stoppable outputs and EMI control.

Technical Context

The CY28346ZC employs two independent PLLs: PLL1 generates CPU clocks with programmable N/R registers via SMBus for fine-grained frequency adjustment (Dial-a-Frequency™), while PLL2 derives PCI, 3V66, and 48 MHz outputs synchronized to the CPU clock or 66 MHz reference input. Spread-spectrum modulation (SSCG) is implemented via SS0–SS2 register bits controlling down-spread (±0.25% to ±1.0%) or center-spread (±0.13% to ±0.50%) modes.

It supports tri-level S2 input for hardware frequency selection, SMBus address D2/D3 for register read/write, and dual power-down modes: asynchronous PD# halts all clocks except SMBus logic, while synchronous CPU_STP# and PCI_STP# disable respective output groups with defined final states (CPUT HIGH / CPUC LOW) and latency ≤2 clock cycles.

Key Specifications

Pinout & Package

Package: 56-pin Thin Shrink Small Outline Package (TSSOP), 12.5 mm × 6.1 mm body, 0.5 mm lead pitch, exposed pad not included.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with ICS9LPR503AGT and Si5338A-D-GM, the CY28346ZC uniquely combines Intel CK408 compliance, tri-level hardware frequency selection, and on-chip Dial-a-Frequency™-enabling both factory-programmed and runtime-adjustable CPU clocks in space-constrained mobile designs without external memory.

Availability

CY28346ZC is available at Aetrix Electronics and suitable for mobile computing, embedded industrial PCs, and medical imaging systems requiring stable component supply, long-term lifecycle support, and validated CK408 timing compliance.

Supply support for CY28346ZC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and sensor technologies for IoT and embedded markets.

The CY28346ZC belongs to Silicon Labs' CK408-compliant clock synthesizer product line, designed specifically for Intel mobile platform reference designs requiring low-power, multi-output, and EMI-optimized timing solutions.

FAQ

What is the function of the S2 pin on the CY28346ZC?

The S2 pin on the CY28346ZC is a tri-level input that determines clock selection mode at power-up: driven HIGH or LOW selects standard frequency tables via S[1:0], while driven to an intermediate voltage (1.0–1.8 V) latches S[2:0] into internal registers for M-state configuration. This enables flexible boot-time clock initialization without requiring external logic.

Does the CY28346ZC support spread-spectrum clocking on all outputs?

No-the CY28346ZC applies spread-spectrum modulation only to clocks derived from PLL1, including CPU outputs and the 3V66_1/VCH pin when configured as 66 MHz (DRCG mode). The 48MUSB, 48MDOT, and REF outputs are fixed-frequency and non-spread-spectrum by design.

How does the CY28346ZC handle CPU clock stopping during CPU_STP# assertion?

When CPU_STP# is asserted LOW, the CY28346ZC synchronously stops CPUT/CPUC outputs after two falling clock edges: CPUT pins drive HIGH at programmed current (Iref × 4 or ×6), while CPUC pins go undriven (LOW via external pull-down). SMBus Byte0 Bit6 and Byte1 Bit6 allow tri-state override of this behavior.

Can the CY28346ZC generate 133 MHz CPU clocks with guaranteed timing margins?

Yes-the CY28346ZC delivers 133 MHz CPU clocks with verified AC parameters: period tolerance ±0.3 ns (7.35–7.65 ns), duty cycle 45–55%, cycle-to-cycle jitter ≤150 ps, and inter-pair skew ≤100 ps-all tested at 0–70 °C with 3.3 V ±5% supply, meeting Intel CK408 requirements for Pentium M/Core Duo platforms.

What is the purpose of the MULT0 and IREF pins on the CY28346ZC?

MULT0 and IREF configure the CPU clock output drive strength: MULT0 selects between 4×Iref (0.7 V swing) or 6×Iref (1.0 V swing); IREF connects to a precision resistor (221 Ω or 475 Ω) referenced to VSSIREF to set base current. This enables board-specific impedance matching to 50 Ω traces without external resistors.