Infineon Technologies CY28346ZXC

Overview

CY28346ZXC from Cypress Semiconductor is a 3.3V clock synthesizer compliant with Intel® CK408 Mobile specifications, generating three differential CPU clocks (66/100/133/200 MHz), ten PCI clocks, and five/six 3.3V 66-MHz clocks. It integrates dual PLLs, SMBus programmability, spread-spectrum EMI reduction, and Dial-a-Frequency™/Dial-a-dB™ tuning for mobile chipset timing.

For engineers reviewing the CY28346ZXC datasheet, CY28346ZXC pinout, CY28346ZXC application, or CY28346ZXC equivalent, key selection criteria include differential CPU clock drive strength (programmable via IREF/VSSIREF), tri-level S2 frequency select input, SMBus register Byte0–Byte9 control of spread spectrum, CPU/PCI stop modes, and 56-pin TSSOP package thermal and routing constraints.

Technical Context

The CY28346ZXC employs two independent PLLs: PLL1 generates CPU clocks with selectable multiplication (N/R registers via SMBus Byte8/Byte9), while PLL2 derives PCI, 3V66, and USB/DOT clocks from the same reference. Frequency selection is determined by hardware pins S2/S1/S0 (tri-level S2) and programmable SMBus registers, enabling dynamic reconfiguration without reset.

It supports synchronous clock disabling via CPU_STP# and PCI_STP# inputs, with configurable behavior per output group (e.g., PCIF clocks can be made free-running or stoppable via SMBus Byte3). Spread spectrum modulation is implemented via SS0–SS2 bits (Byte5/Byte4), offering down-spread (0.25–1.0%) or center-spread (±0.13–±0.50%) modes per Table 3.

Key Specifications

Pinout & Package

Package: 56-pin TSSOP (Thin Shrink Small Outline Package), 0.5 mm pitch, JEDEC MO-153AC compliant, body size 14.0 × 6.1 mm, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with ICS9LPRS355AKLFT and PI6C20400LEX, the CY28346ZXC uniquely combines Intel CK408 compliance, tri-level hardware frequency selection, SMBus-accessible DAF/DA-dB tuning, and integrated 48-MHz USB/DOT clocks-making it optimal for mobile x86 platforms requiring field-programmable EMI control and multi-standard clock distribution.

Availability

CY28346ZXC is available at Aetrix Electronics and suitable for mobile chipset timing, embedded x86 platform clocking, and low-EMI notebook designs requiring stable component supply, long-lifecycle support, and traceable sourcing.

Supply support for CY28346ZXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) designs high-performance timing, memory, and programmable logic solutions for computing, automotive, and industrial markets.

The CY28346 belongs to Cypress's CK408-compliant clock synthesizer product line, engineered specifically for Intel mobile platform reference designs requiring differential CPU clocks, flexible PCI timing, and integrated EMI reduction.

FAQ

What is the function of the VTT_PG# pin?

VTT_PG# is an active-low input that latches the logic states of S2, S1, S0, and MULT0 at power-up. It must be driven LOW before VDD reaches 2.7V to ensure correct initialization of the frequency select and current multiplier settings. If left floating or HIGH during power ramp, the device may enter an undefined frequency mode.

How does Dial-a-Frequency™ work without affecting other clocks?

Dial-a-Frequency™ modifies only the N and R divider values feeding PLL1, which generates the CPU clocks. Since PCI, 3V66, and USB clocks derive from PLL2 (locked to the same XIN reference), their frequencies remain fixed relative to the original 66-MHz or 14.318-MHz source-preserving timing relationships critical for synchronous bus operation.

Can the 48MUSB and 48MDOT outputs be disabled independently?

Yes. SMBus Byte3 Bits 7 and 6 directly control 48MDOT and 48MUSB enable/disable states. Writing '0' to Bit7 forces 48MDOT LOW; writing '0' to Bit6 forces 48MUSB LOW. Both outputs default to enabled (logic 1) at power-up and retain state across SMBus writes without requiring full register reinitialization.

What termination is required for differential CPU clock outputs?

The CY28346ZXC differential CPU outputs (CPUT/CPUC) require 100Ω differential termination. Per Figures 1 and 2, this is implemented as two 50Ω resistors to VDD (for 1.0V swing) or to ground (for 0.7V swing), with 2pF measurement capacitance. The IREF/VSSIREF resistor sets output current to match the selected termination and voltage swing.