Infineon Technologies CY28405OXC

Overview

CY28405OXC from Cypress Semiconductor is a CK409-compliant clock synthesizer designed for Intel Springdale/Prescott platform timing control. It delivers three differential CPU clock pairs (100–200 MHz), nine 33-MHz PCI clocks, four 66-MHz 3V66 clocks (one selectable to 48 MHz), two 48-MHz USB clocks, two 14.318-MHz REF clocks, and supports SMBus/I²C configuration with spread-spectrum EMI reduction.

For engineers reviewing the CY28405OXC datasheet, CY28405OXC pinout, CY28405OXC application, or CY28405OXC equivalent, this device serves as a multi-output, programmable clock source for desktop motherboard designs requiring precise frequency selection, flexible output enable/disable, and hardware strapping or serial interface control of clock domains.

Technical Context

The CY28405OXC integrates two PLLs: PLL1 generates the core VCO frequency (24–48 MHz × integer gear ratio) for CPU/3V66/PCI outputs, while PLL2 provides independent 48-MHz USB/REF clocks. Frequency selection is latched via five FS[A:E] inputs synchronized to VTT_PWRGD# assertion, enabling stable boot-time clock configuration before processor voltage stabilization.

It implements a dual-control architecture: hardware strapping (MODE, SELVCH, FS pins) sets primary operating mode and default frequencies, while SMBus (7-bit slave address D2h) allows dynamic runtime reconfiguration of output enables, drive strength, skew, and spread-spectrum parameters across ten user-accessible registers.

Key Specifications

Pinout & Package

48-pin SSOP package (standard JEDEC MO-153), 0.635 mm pitch, body size 10.2 × 12.8 mm. Thermal pad not present; requires standard SSOP PCB footprint and reflow profile.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with IDT 87010AGLFT and ICS954202AF, the CY28405OXC uniquely combines CK409-specific hardware strapping, differential CPU clock generation, and full SMBus register access-making it irreplaceable for Intel Springdale/Prescott motherboard designs requiring boot-time frequency determinism and post-boot flexibility.

Availability

CY28405OXC is available at Aetrix Electronics and suitable for desktop motherboard design, Intel platform validation, and industrial embedded computing applications requiring stable component supply and long-term lifecycle support.

Supply support for CY28405OXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a fabless semiconductor company specializing in high-performance timing, memory, and programmable logic solutions for computing and communications infrastructure.

The CY28xxx clock synthesizer product line was engineered specifically for Intel chipset platforms-including Springdale, Grantsdale, and Alderwood-delivering CK409/CK410-compliant timing with hardware strapping and SMBus configurability.

FAQ

What is the function of the VTT_PWRGD# pin?

VTT_PWRGD# is an active-low input that signals stable processor VTT voltage. The CY28405OXC samples the FS[A:E] frequency select pins only upon detecting a valid low-to-high transition on this pin, ensuring clock configuration occurs after core voltage stabilization and preventing boot-time clock glitches.

Can the 3V66_3/VCH pin be configured exclusively via SMBus?

Yes-the 3V66_3/VCH pin defaults to 66 MHz at power-up but can be switched to 48 MHz either by strapping it LOW via external resistor (SELVCH mode) or by writing '1' to bit 5 of Control Register 5 (Byte 5) over SMBus, overriding the hardware setting without physical modification.

Does the CY28405OXC support PCIe reference clock generation?

No-it does not generate PCIe 100-MHz differential reference clocks. Its CPU outputs are optimized for Intel Pentium 4 front-side bus timing (100–200 MHz differential), and its USB/REF outputs are fixed 48/14.318 MHz single-ended; PCIe refclk requires separate compliant oscillator or buffer.

How many SMBus addresses does the CY28405OXC support?

The device uses a fixed 7-bit SMBus slave address of 0xD2 (11010010b). No address pins or hardware strapping options exist to change this address, so only one CY28405OXC may reside on a given SMBus segment unless isolated via multiplexer.