Infineon Technologies CY28409OXC

Overview

CY28409 from Cypress Semiconductor is a clock synthesizer IC designed for Intel Pentium 4–class CPU platforms, generating differential CPU clocks (up to 400 MHz), a differential SRC clock, ten 33-MHz PCI outputs, five 66-MHz 3V66 outputs (one selectable as 48 MHz), and two fixed 48-MHz USB clocks-all from a single 14.318-MHz crystal reference. It operates at 3.3 V and supports I²C-based configuration with readback.

For engineers reviewing the CY28409 datasheet, CY28409 pinout, CY28409 application, or CY28409 equivalent, this device is selected for motherboard timing subsystems requiring precise frequency selection via FS_A/FS_B, spread-spectrum EMI reduction, and per-output enable/disable control through SMBus registers.

Technical Context

The CY28409 integrates two PLLs: PLL1 locks to the 14.318-MHz crystal (XIN/XOUT) to generate core frequencies, while PLL2 derives SRC and CPU clocks from PLL1's output. Frequency selection is determined by FS_A/FS_B logic levels sampled on VTT_PWRGD# assertion, enabling discrete CPU clock modes (100/133/200/266/400 MHz) and dual SRC options (100/200 MHz).

It implements a full SMBus 2.0–compliant serial interface (SCLK/SDATA) with slave address 0xD2, supporting byte/block reads/writes to eight control registers. Output drive strength, stop behavior during STP# events, and individual buffer enables (e.g., CPUT0–CPUT2, PCI0–PCI6) are all software-configurable-not hardwired.

Key Specifications

Pinout & Package

Available in 56-pin SSOP and TSSOP packages with 0.5-mm pitch; thermally enhanced for desktop motherboard applications requiring low EMI and stable clock distribution.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with IDT 87010AGLFT and ICS 952002AF, the CY28409 uniquely combines differential CPU clock generation up to 400 MHz, SMBus-configurable VCH mode, and Lexmark spread spectrum-making it irreplaceable for legacy Pentium 4 motherboard designs requiring full BIOS control and EMI compliance.

Availability

CY28409 is available at Aetrix Electronics and suitable for desktop motherboard design, Intel platform validation, and legacy PCI/AGP system refurbishment requiring stable component supply and long-term obsolescence mitigation.

Supply support for CY28409 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor, now part of Infineon Technologies, is a fabless semiconductor company specializing in timing, memory, and programmable solutions for computing and communications infrastructure.

The CY28xxx clock synthesizer product line was engineered specifically for Intel-compatible x86 platform timing, emphasizing BIOS-controllable frequency selection, differential signaling integrity, and EMI-aware clock synthesis.

FAQ

What crystal specifications are mandatory for reliable CY28409 operation?

The CY28409 requires a 14.31818-MHz AT-cut parallel-resonant crystal with 20-pF load capacitance, ≤0.1 mW drive level, ≤5 pF shunt capacitance, and ±50 ppm initial tolerance. Substituting a series-resonant crystal causes ≥300-ppm frequency error and violates stability specs.

How does VTT_PWRGD# affect CPU frequency selection?

VTT_PWRGD# is a level-sensitive strobe that latches FS_A and FS_B logic states at power-up. Once sampled LOW, the chip ignores further transitions on FS_A/FS_B until next power cycle-ensuring deterministic CPU clock mode selection before processor initialization begins.

Can the CY28409 generate non-standard frequencies like 166 MHz or 333 MHz?

No. The CY28409 supports only the discrete CPU frequencies defined in Tables 1 and 2: 100, 133, 200, 266, and 400 MHz. These are generated via integer PLL multiplication of the 14.318-MHz reference; fractional-N synthesis is not implemented.

Is SMBus communication possible after system boot, or only during initialization?

SMBus communication is permitted post-boot but limited to output enable/disable and drive-strength changes. Frequency reconfiguration (e.g., changing CPU clock mode) requires power cycle because FS_A/FS_B sampling occurs only once at VTT_PWRGD# assertion.