Skyworks Solutions Inc. CY28409OXCT

Overview

CY28409OXCT from Cypress Semiconductor is a clock synthesizer IC designed for Intel Pentium 4–based desktop platforms, generating differential CPU clocks (up to 400 MHz), a differential SRC clock (100/200 MHz), ten 33-MHz PCI outputs, five 66-MHz 3V66 clocks, and dual 48-MHz USB clocks-all from a single 14.318-MHz crystal reference. It operates at 3.3 V and supports SMBus-based configuration and spread-spectrum EMI reduction.

For engineers reviewing the CY28409OXCT datasheet, CY28409OXCT pinout, CY28409OXCT application, or CY28409OXCT equivalent, key selection criteria include differential CPU clock pair count (3), I²C/SMBus register readback capability, selectable 48/66-MHz VCH output, PCI_STP#-synchronized clock gating, and Lexmark-specified spread-spectrum profile compliance.

Technical Context

The CY28409OXCT integrates two PLLs: PLL1 generates the 100/200-MHz SRC clock and feeds PLL2, which produces CPU clocks (100–400 MHz) and 66-MHz 3V66 outputs. Frequency selection is controlled via FS_A/FS_B pins latched on VTT_PWRGD# assertion, with test mode triggered by mid-level FS_B.

Its serial interface uses SMBus-compatible SCLK/SDATA (7-bit slave address 0xD2) to enable/disable individual outputs, configure drive strength, set stop/power-down behavior per clock group (CPU, SRC, PCI, USB), and toggle spread spectrum-register changes occur only at system initialization, not runtime.

Key Specifications

Pinout & Package

The CY28409OXCT is packaged in a 56-pin SSOP/TSSOP (JEDEC MO-153) with exposed pad option; pin functions are validated per Cypress Document #38-07445 Rev. *D.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with IDT72V223L and ICS952002AGT, the CY28409OXCT uniquely delivers triple differential CPU clock pairs with guaranteed skew matching, Lexmark-specified spread spectrum, and VCH-mode flexibility-making it the only drop-in solution for validated Pentium 4 reference designs requiring full FSB timing compliance.

Availability

CY28409OXCT is available at Aetrix Electronics and suitable for desktop motherboard design, Intel Pentium 4 platform validation, and industrial PC timing applications requiring stable component supply and long-term lifecycle support.

Supply support for CY28409OXCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor, now part of Infineon Technologies, is a fabless semiconductor company specializing in timing, memory, and programmable solutions for computing and industrial markets.

The CY28xxx clock synthesizer product line was engineered specifically for Intel Pentium 4 and early Core architecture platforms, emphasizing differential clock fidelity, SMBus configurability, and EMI-compliant spread spectrum for desktop and embedded PC applications.

FAQ

What crystal specifications are mandatory for CY28409OXCT operation?

The CY28409OXCT requires a 14.31818-MHz parallel-resonant AT-cut crystal with 20-pF load capacitance, maximum 0.1-mW drive level, and ≤50-ppm initial tolerance. Using a series-resonant crystal causes ≥300-ppm frequency error and violates timing specs. Trim capacitors must be placed in series with the crystal per Figure 1 in the datasheet.

How does VTT_PWRGD# affect CPU frequency selection?

VTT_PWRGD# is a level-sensitive strobe that latches FS_A and FS_B logic states at power-up. Once sampled LOW (indicating stable VTT voltage), the device ignores further transitions on FS_A, FS_B, and VTT_PWRGD#. If FS_B is mid-level during sampling, the device enters Test Clock Mode-requiring power cycle with FS_B HIGH or LOW to exit.

Can the CY28409OXCT generate clocks for both PCI and USB simultaneously?

Yes. The CY28409OXCT concurrently delivers seven 33-MHz PCI clocks (PCI0–PCI6), three free-running PCIF clocks, and two 48-MHz USB clocks (USB_48 and DOT_48). All are generated from the same 66-MHz 3V66 source, with USB outputs independently enableable via Registers 4 and 5.

Is SMBus communication possible after system initialization?

SMBus operations (read/write) are supported only during system initialization-not during active operation. The interface cannot be used for runtime power management because register updates require full clock tree reset. Configuration must be completed before CPU execution begins to avoid timing violations.