Infineon Technologies CY28409ZXC

Overview

CY28409ZXC from Cypress Semiconductor is a programmable clock synthesizer designed for Intel Pentium 4–class CPU platforms, delivering three differential 100/133/200/266/400 MHz CPU clock pairs, one differential 100/200 MHz SRC clock, ten 33 MHz PCI clocks, five 66 MHz 3V66 clocks (one selectable as 48 MHz), and two fixed 48 MHz USB clocks - all from a single 14.318 MHz crystal reference under 3.3V supply.

For engineers reviewing the CY28409ZXC datasheet, CY28409ZXC pinout, CY28409ZXC application, or CY28409ZXC equivalent, this device supports SMBus-configurable output enables, spread-spectrum EMI reduction, per-output drive strength control, and VTT_PWRGD#-synchronized frequency selection - critical for desktop motherboard timing compliance and power-state coordination.

Technical Context

The CY28409ZXC integrates two PLLs: PLL1 generates the core 100/200 MHz SRC clock and feeds PLL2, which produces CPU, 3V66, PCI, and USB clocks. Frequency selection is latched via FS_A/FS_B inputs synchronized to VTT_PWRGD#, enabling stable boot-time configuration without run-time glitches.

Its I²C-compatible serial interface (SCLK/SDATA) allows dynamic enable/disable of individual outputs (e.g., CPUT0–CPUT2, PCI0–PCI6, USB_48) and configuration of spread spectrum, drive strength, and stop behavior during PCI_STP# assertion - supporting both hardware- and software-controlled power management.

Key Specifications

Pinout & Package

56-pin SSOP/TSSOP package with separate power/ground domains per functional block (CPU, SRC, 3V66, PCI, USB, REF) and integrated pull-up/pull-down resistors on select control pins (PD#, CPU_STP#, PCI_STP#, VTT_PWRGD#).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with IDT 87351AGLFT and ICS 952002AF, the CY28409ZXC uniquely delivers differential CPU clock pairs with VTT_PWRGD#-synchronized frequency selection and full SMBus readback - making it irreplaceable for Pentium 4 motherboard designs requiring EMI-compliant, glitch-free boot and runtime clock management.

Availability

CY28409ZXC is available at Aetrix Electronics and suitable for desktop motherboard design, Intel Pentium 4 platform development, and legacy PCI/AGP system upgrades requiring stable component supply and long-term lifecycle support.

Supply support for CY28409ZXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a fabless semiconductor company specializing in timing, memory, and programmable logic solutions for computing and industrial applications.

The CY28409 belongs to Cypress's high-precision clock synthesizer product line, engineered specifically for Intel Pentium 4–era desktop and workstation platforms requiring differential CPU clocking, spread-spectrum EMI control, and robust power-state coordination.

FAQ

What crystal specifications are mandatory for CY28409ZXC operation?

The CY28409ZXC requires a 14.31818 MHz parallel-resonant AT-cut crystal with 20 pF load capacitance, maximum 0.1 mW drive level, and ≤50 ppm initial tolerance. Using a series-resonant crystal causes frequency error and violates ppm specification due to 300-ppm loading mismatch.

How does VTT_PWRGD# affect CPU frequency selection?

VTT_PWRGD# is a level-sensitive strobe that latches FS_A and FS_B logic states only once - when sampled LOW. This ensures CPU clock frequency is selected precisely when the processor's VTT voltage rail stabilizes, preventing boot-time clock misconfiguration and guaranteeing deterministic startup behavior.

Can all clock outputs be disabled independently?

Yes. Each clock output group - including CPUT0–CPUT2, SRCT/SRCC, PCI0–PCI6, USB_48/DOT_48, and REF_0/REF_1 - has dedicated enable/disable bits in registers 1–6. Disabling an output places it in high-impedance state, reducing system noise and standby current without affecting other outputs.

Is spread-spectrum clocking configurable per output or global?

Spread-spectrum is global and controlled by Register 6 Bit 2. When enabled, it applies the Lexmark-profile modulation to all generated clocks (CPU, SRC, 3V66, PCI, USB) simultaneously. There is no per-output spread-spectrum control; modulation depth and frequency are fixed per datasheet specification.