Infineon Technologies CY28410ZXC

Overview

CY28410ZXC from Cypress Semiconductor is a clock generator IC compliant with Intel® CK410 specification, designed for Intel Grantsdale chipset platforms. It delivers differential CPU clocks up to 266 MHz, 100-MHz differential SRC clocks, 96-MHz dot clock, 48-MHz USB, and 33-MHz PCI clocks-all from a single 14.318-MHz crystal input. It supports I²C programmability, spread-spectrum EMI reduction, and operates on a 3.3V supply in 56-pin SSOP/TSSOP.

For engineers reviewing the CY28410ZXC datasheet, CY28410ZXC pinout, CY28410ZXC application, or CY28410ZXC equivalent, key selection considerations include Intel P4/Tejas CPU clocking compliance, differential output drive capability, frequency select pin logic mapping (FS_A/B/C), I²C register control of individual output enables, and VTT_PWRGD#-latched configuration timing.

Technical Context

The CY28410ZXC integrates two PLLs: PLL1 generates the 14.318-MHz reference-derived CPU and SRC clocks, while PLL2 produces the fixed 96-MHz dot clock and 48-MHz USB clock. All outputs are fully configurable via three 3.3V-tolerant frequency select pins (FS_A, FS_B, FS_C) sampled synchronously on VTT_PWRGD# assertion.

It implements an SMBus-compatible I²C interface (SCLK/SDATA) with slave address 0xD2h, supporting byte/block read/write operations to eight control registers that enable/disable individual outputs (e.g., CPUT0–CPUT2, SRCT1–SRCT7, PCI0–PCI5), configure spread spectrum, and set drive strength-without requiring external configuration EEPROM.

Key Specifications

Pinout & Package

Package: 56-pin SSOP and TSSOP (lead-free, RoHS-compliant); thermal pad not present; body size 18.4 mm × 7.5 mm; pitch 0.5 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with IDT 87010AGLFT and ICS954202AF, the CY28410ZXC uniquely combines Intel CK410 compliance, 266-MHz CPU support, dedicated 96-MHz dot clock, and full I²C programmability-making it the only drop-in solution for Grantsdale reference designs requiring full feature parity.

Availability

CY28410ZXC is available at Aetrix Electronics and suitable for desktop motherboard design, industrial embedded PCs, SATA storage subsystems, and legacy peripheral timing bridges requiring stable component supply and long-term lifecycle support.

Supply support for CY28410ZXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a U.S.-based semiconductor company specializing in timing, memory, and programmable solutions for computing and communications infrastructure.

The CY28410 belongs to Cypress's CK410-compliant clock generator product line, engineered specifically to replace discrete clock trees in Intel Grantsdale-based platforms while delivering guaranteed timing margin and EMI performance.

FAQ

What crystal specifications are mandatory for CY28410ZXC operation?

The CY28410ZXC requires a 14.31818-MHz parallel-resonant AT-cut crystal with 20-pF load capacitance, maximum 0.1-mW drive level, and ≤35-ppm initial tolerance. Using a series-resonant crystal causes frequency error exceeding ±300 ppm and violates Intel CK410 timing specs.

How does VTT_PWRGD# affect configuration and power-down behavior?

VTT_PWRGD# serves two roles: first, it latches FS_A/B/C pin states to select CPU/SRC frequencies at power-up; second, when driven high after initialization, it triggers synchronous shutdown of all STOPPABLE outputs (PCI, PCIF, SRC) without glitches-enabling clean power-state transitions in ACPI S3/S4.

Can the 96-MHz dot clock be disabled or repurposed?

Yes-the DOT96T/DOT96C outputs can be disabled independently via Control Register 1 (bit 6). However, they cannot be reconfigured to other frequencies; the 96-MHz path is hardwired and not programmable. Disabling frees board routing but does not alter internal PLL operation.

Is I²C communication possible after system boot without resetting the device?

Yes-I²C remains fully functional after power-up and VTT_PWRGD# assertion. The interface supports runtime output enable/disable, spread-spectrum toggling, and drive-strength changes without interrupting existing clock outputs or requiring device reset.