Infineon Technologies CY28411OXC-1

Overview

CY28411OXC-1 from Cypress Semiconductor is a programmable clock generator compliant with Intel CK410M specification, designed for Intel Alviso chipset platforms and Pentium-M CPU systems. It delivers 100-MHz differential SRC clocks, 96-MHz differential dot clock, 48-MHz USB clock, 33-MHz PCI clock, and 14.318-MHz reference clock-all from a single 14.318-MHz crystal input under 3.3V supply.

For engineers reviewing the CY28411OXC-1 datasheet, CY28411OXC-1 pinout, CY28411OXC-1 application, or CY28411OXC-1 equivalent, key selection criteria include I²C-configurable output enables, selectable CPU frequencies (100/133/200/266 MHz), Lexmark-specified spread-spectrum EMI reduction, differential clock pair routing support, and VTT_PWRGD#-synchronized frequency select latching.

Technical Context

The CY28411OXC-1 integrates two PLLs: PLL1 generates the 100-MHz SRC base frequency from the 14.318-MHz crystal reference, while PLL2 synthesizes CPU clock frequencies via integer-N division of PLL1 output. Frequency selection is determined by FS_A/FS_B/FS_C logic levels sampled once on VTT_PWRGD# assertion-enabling deterministic boot-time configuration without runtime reconfiguration.

All differential outputs (CPUT/CPUC, SRCT/SRCC, DOT96T/DOT96C, SRC4_SATAT/SRC4_SATAC) use current-mode logic (CML)-compatible drivers with 50-Ω internal termination. The I²C interface (SCLK/SDATA) supports byte/block read/write to eight control registers for per-output enable/disable, spread-spectrum activation, and stop-drive mode configuration-though register writes occur only during system initialization, not dynamic power management.

Key Specifications

Pinout & Package

Package: 56-pin SSOP/TSSOP (CY28411OXC-1 denotes SSOP variant). Pin assignments validated per Cypress Document #38-07694 Rev. *B, Pages 2–3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with IDT 8T49N241 and ICS9LPRS495, the CY28411OXC-1 uniquely combines Intel CK410M compliance, differential CPU/SRC clock pairs, I²C-configurable enable control, and Lexmark-specified spread spectrum-making it irreplaceable for Alviso-based notebook designs requiring full feature parity.

Availability

CY28411OXC-1 is available at Aetrix Electronics and suitable for mobile notebook platforms, Intel Pentium-M desktop motherboards, SATA storage controllers, and industrial PCI expansion systems requiring stable component supply and long-term lifecycle support.

Supply support for CY28411OXC-1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a fabless semiconductor company specializing in timing, memory, and programmable logic solutions for computing and communications markets.

The CY28411 product line was developed specifically to address Intel chipset clocking requirements-including CK410M compliance, VTT-synchronized frequency selection, and integrated spread spectrum-targeting mobile and desktop platform design teams.

FAQ

What crystal specifications are required for CY28411OXC-1?

The CY28411OXC-1 requires a 14.31818-MHz parallel-resonant AT-cut crystal with 20-pF load capacitance, ≤0.1-mW drive level, and ≤35-ppm initial tolerance. Substituting a series-resonant crystal causes ≥300-ppm frequency error and violates ppm specifications due to incorrect loading.

How does VTT_PWRGD# affect frequency selection behavior?

VTT_PWRGD# acts as a one-shot latch: it samples FS_A/FS_B/FS_C logic levels only once upon transition to active-low, freezing CPU frequency selection permanently until next power cycle. Subsequent transitions on those pins are ignored unless test mode is entered via FS_C pull-down during VTT_PWRGD# assertion.

Can all differential outputs be disabled independently?

Yes-Control Registers 0 through 5 provide individual enable/disable bits for each differential output pair (CPUT/CPUC, SRCT/SRCC, DOT96T/DOT96C, SRC4_SATAT/SRC4_SATAC), allowing selective shutdown to reduce system power without affecting other clock domains.

Is spread spectrum applied to all clock outputs by default?

No-spread spectrum is disabled by default. It must be explicitly enabled per output group via Control Register 0 bit 0 (CPUT/C SRCT/C PCIF PCI Spread Spectrum Enable). Only outputs with this bit set will apply the Lexmark-optimized ±0.25% center-spread modulation.