Infineon Technologies CY28411OXC-1T

Overview

CY28411OXC-1T from Cypress Semiconductor is a programmable clock generator IC designed for Intel Alviso chipset platforms, delivering differential CPU clocks (up to 266 MHz), 100-MHz differential SRC clocks, 96-MHz dot clock, 48-MHz USB, and 33-MHz PCI timing - all from a single 14.318-MHz crystal input. It supports I²C configuration, spread-spectrum EMI reduction, and CPU stop/power-down control for Pentium-M systems.

For engineers reviewing the CY28411OXC-1T datasheet, CY28411OXC-1T pinout, CY28411OXC-1T application, or CY28411OXC-1T equivalent, key selection criteria include differential output compliance with Intel CK410M, I²C register readback capability, selectable CPU frequency modes via FS_A/B/C, and dedicated SATA reference clock outputs (SRC4_SATAT/SATAC).

Technical Context

The CY28411OXC-1T integrates two PLLs: PLL1 generates the 14.318-MHz reference and CPU clocks; PLL2 synthesizes SRC, PCI, and USB frequencies. All differential outputs use current-mode logic (CML) with 50-Ω internal termination and support 3.3-V operation only.

Frequency selection is latched on VTT_PWRGD# assertion using three 3.3-V-tolerant FS inputs, enabling eight discrete CPU clock modes (100/133/200/266 MHz). The I²C interface (slave address D2h) allows runtime enable/disable of individual outputs via seven control registers, but does not support dynamic frequency reconfiguration during operation.

Key Specifications

Pinout & Package

Package: 56-pin SSOP/TSSOP (JEDEC MO-153), 0.5-mm pitch, body size 10.2 × 12.8 mm. Thermal pad not present; requires standard PCB thermal relief for 3.3-V power pins.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with IDT 87021AGLFT and ICS954202AF, the CY28411OXC-1T uniquely delivers CK410M-aligned CPU/SRC timing, hardware-synchronized stop control, and SATA-optimized differential outputs - making it irreplaceable in validated Alviso designs requiring full Intel platform compliance.

Availability

CY28411OXC-1T is available at Aetrix Electronics and suitable for Intel Alviso notebook platforms, SATA host controller timing, USB 2.0 peripheral hubs, and PCI legacy expansion slot applications requiring stable component supply and long-term industrial availability.

Supply support for CY28411OXC-1T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon) designs high-performance timing, memory, and programmable logic solutions for computing and communications infrastructure.

The CY28411 product line targets Intel chipset-specific clock synthesis, emphasizing CK410M compliance, differential signal integrity, and platform-level power sequencing integration.

FAQ

What crystal specifications are mandatory for CY28411OXC-1T operation?

The device requires a 14.31818 MHz parallel-resonant AT-cut crystal with 20-pF load capacitance, ≤0.1 mW drive level, and ≤35 ppm initial tolerance. Using a series-resonant crystal causes >300 ppm frequency error and violates Intel CK410M timing specs - no workaround exists.

Can CPU clock frequency be changed dynamically after system boot?

No. CPU frequency is latched once at VTT_PWRGD# assertion and cannot be altered without full power cycle. The FS_A/B/C pins are sampled only during this one-time event; subsequent changes have no effect unless VTT_PWRGD# is reasserted.

Does CY28411OXC-1T support spread-spectrum clocking on all outputs?

Spread spectrum is applied only to the 100-MHz SRC outputs (SRCT0–SRCT7, SRCC0–SRCC7) using the Lexmark profile. CPU, DOT96, USB_48, and PCI clocks operate at fixed frequencies with no modulation capability.

How is I²C register access used to manage power states?

I²C controls output enable/disable (e.g., disabling unused SRC outputs to reduce power) and spread-spectrum on/off, but does not manage CPU_STP#/PCI_STP# behavior. Hardware strobes remain the sole method for synchronous clock gating during sleep transitions.