Skyworks Solutions Inc. CY28442ZXC-2

Overview

CY28442ZXC-2 from Silicon Labs is a programmable clock generator IC designed specifically for Intel® Alviso chipset platforms, delivering synchronized differential clock outputs including 100 MHz SRC, 96 MHz dot clock, 48 MHz USB, and 33 MHz PCI. It integrates three PLLs (CPU, SRC, and fixed-frequency), supports I²C configuration with readback, and implements spread-spectrum clocking for EMI reduction in notebook and mobile computing systems.

For engineers reviewing the CY28442ZXC-2 datasheet, CY28442ZXC-2 pinout, CY28442ZXC-2 application, or CY28442ZXC-2 equivalent, key selection considerations include Intel CK410M compliance, selectable CPU frequencies (100/133/166/200 MHz), differential output drive capability, SMBus register control of individual clock enables/stops, and 56-pin TSSOP package compatibility with Intel Pentium-M reference designs.

Technical Context

The CY28442ZXC-2 employs three independent PLLs: PLL1 generates CPU clocks (100–200 MHz) with spread-spectrum support; PLL2 produces 100 MHz serial reference clocks (SRC); and PLL3 delivers fixed 96 MHz dot clock and 48 MHz USB clocks. All PLLs lock to a 14.318 MHz parallel-resonant crystal input.

It features dual active-low control interfaces: CPU_STP# synchronously stops CPU outputs (CPUT/CPUC) within ≤6 CPU cycles, while CLKREQA#/CLKREQB# independently enable/disable selected SRC outputs via SMBus-configurable mapping. Power sequencing is simplified by VTT_PWRGD# latching frequency select inputs (FS_A/B/C) at power-up.

Key Specifications

Pinout & Package

Package: 56-pin TSSOP (0.5 mm pitch), RoHS-compliant, moisture sensitivity level 1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with ICS9LPR503AGT and PI6C20400LEX, the CY28442ZXC-2 uniquely integrates triple-PLL synthesis, Intel CK410M compliance, and programmable spread spectrum in a single 56-pin TSSOP package - making it irreplaceable for Alviso-based designs requiring full clock generation capability.

Availability

CY28442ZXC-2 is available at Aetrix Electronics and suitable for mobile computing platforms, Intel chipset reference designs, flat-panel display timing subsystems, USB 2.0 host controller interfaces, and embedded notebook applications requiring stable component supply and long-term lifecycle support.

Supply support for CY28442ZXC-2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and sensor solutions, with leadership in precision clock generation and low-power mixed-signal ICs.

The CY28442ZXC-2 belongs to Silicon Labs' CK410M-compliant clock generator product line, engineered to meet Intel's stringent timing, jitter, and EMI requirements for mobile Pentium-M platforms.

FAQ

What is the primary function of the CY28442ZXC-2 in Intel Alviso-based systems?

The CY28442ZXC-2 serves as the central clock synthesizer, generating all critical platform clocks-including CPU, SRC, dot clock, USB, and PCI-from a single 14.318 MHz crystal. It ensures precise phase alignment, low jitter, and CK410M compliance required for stable operation of Intel Alviso chipsets and Pentium-M processors. Its triple-PLL architecture enables independent frequency domains without interference.

Does the CY28442ZXC-2 support spread-spectrum clocking, and how is it configured?

Yes, the CY28442ZXC-2 supports programmable spread-spectrum clocking on its 96/100 MHz differential outputs. Configuration is done via SMBus register Byte 9, which allows selection of 16 different spread profiles ranging from ±0.25% to ±1.5% modulation depth. The default setting is –0.8%, optimized for Lexmark EMI reduction targets in notebook applications.

How does the CY28442ZXC-2 handle CPU frequency selection?

The CY28442ZXC-2 uses three hardware straps-FS_A, FS_B, and FS_C-to select CPU frequencies (100/133/166/200 MHz) at power-up. These inputs are latched on the falling edge of VTT_PWRGD#, after which further changes are ignored unless test mode is entered. The mapping is defined in Table 1 of the datasheet and cannot be altered dynamically during operation.

Can the CY28442ZXC-2 generate both 96 MHz and 100 MHz dot clocks simultaneously?

No, the CY28442ZXC-2 generates either 96 MHz or 100 MHz on the 96_100_SSC outputs, selected via hardware (PCIF1/96_100_SEL pin) or software (SMBus register Byte 9). The DOT96T/C outputs are fixed at 96 MHz and cannot be reconfigured. Simultaneous 96/100 MHz operation is not supported - the device operates in one mode at a time.

What is the role of the CLKREQA# and CLKREQB# pins on the CY28442ZXC-2?

CLKREQA# and CLKREQB# are active-low, debounced control inputs that enable or disable specific SRC clock outputs (e.g., SRCT1–SRCT7). Their assignment is configurable via SMBus register Byte 8, allowing designers to map each request signal to up to four SRC pairs. This provides flexible, hardware-assisted power gating of serial reference clocks without requiring processor intervention.