Infineon Technologies CY28RS480OXC

Overview

CY28RS480 from Cypress Semiconductor is a clock generator IC designed specifically for the AMD ATI RS480 chipset, providing synchronized, low-jitter differential and single-ended clocks including 200-MHz CPU pairs, 100-MHz SRC, 66-MHz HyperTransport, 48-MHz USB, 33-MHz PCI, and 14.318-MHz REF outputs. It integrates I²C programmability, spread-spectrum EMI reduction, and per-output enable/disable control for desktop motherboard timing.

For engineers reviewing the CY28RS480 datasheet, CY28RS480 pinout, CY28RS480 application, or CY28RS480 equivalent, key selection criteria include differential output compliance (AMD K8/Intel Type-X/Type-5), I²C register-level control of clock enables and drive strength, spread-spectrum configuration, and multi-rail 3.3V power domain isolation (VDD_CPU, VDD_SRC, VDD_PCI, etc.).

Technical Context

The CY28RS480 uses a dual-PLL architecture: one PLL locks to the 14.318-MHz crystal input (XIN/XOUT) to generate the CPU and REF clocks, while a second PLL synthesizes the 100-MHz SRC and 66-MHz HTT66 clocks. All outputs are buffered with Intel- and AMD-compliant drive strengths and termination.

I²C interface (SCLK/SDATA) supports byte/block read/write operations at slave address D2h, enabling runtime configuration of output enables, spread-spectrum depth (–0.35% or –0.50%), drive strength (1x/2x), and CLKREQ#-controlled stop modes - all without requiring system reset.

Key Specifications

Pinout & Package

Package: 56-pin SSOP/TSSOP (0.209" body width, 0.025" pitch). Pin assignments validated per Cypress Document #38-07638 Rev. *C, Pages 2–3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with ICS952006AGT and ICS952012AGT, the CY28RS480 uniquely delivers eight isolated power domains, CLKREQ#-hardware clock gating, and I²C readback - critical for RS480-specific EMI compliance, BIOS tuning, and Minicard slot control.

Availability

CY28RS480 is available at Aetrix Electronics and suitable for desktop motherboard timing, AMD platform reference designs, embedded industrial PCs, and legacy expansion card support requiring stable component supply and long-lifecycle availability.

Supply support for CY28RS480 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a fabless semiconductor company specializing in timing, memory, microcontrollers, and USB solutions for computing and industrial markets.

The CY28RS480 belongs to Cypress's high-precision clock generator product line, engineered specifically to meet AMD chipset timing specifications, EMI requirements, and platform validation needs for desktop and embedded systems.

FAQ

What crystal specifications are mandatory for reliable CY28RS480 operation?

The CY28RS480 requires a 14.31818-MHz parallel-resonant AT-cut crystal with 20-pF load capacitance, ≤35-ppm initial tolerance, ≤30-ppm temperature stability, and ≤5-ppm aging. Substituting a series-resonant crystal causes frequency error (~300 ppm) and violates timing specs. External trim capacitors must be ~33 pF each to achieve correct loading.

How does the CLKREQ# interface control SRC clock outputs?

CLKREQ#0 and CLKREQ#1 are asynchronous, debounced active-low inputs that gate selected SRC outputs (SRCT/C[0:5]) based on settings in Control Registers 4 and 5. When asserted, outputs stop after next transition with SRCT=High and SRCC=Low. The control is hardware-asserted, eliminating software latency and ensuring deterministic clock gating for Minicard compliance.

Can the CY28RS480 generate non-standard frequencies like 125 MHz or 250 MHz?

No. The CY28RS480 is a fixed-function generator with hardwired PLL ratios optimized for AMD RS480 platform clocks: 200 MHz (CPU), 100 MHz (SRC), 66 MHz (HTT), 48 MHz (USB), 33 MHz (PCI), and 14.318 MHz (REF). It lacks programmable dividers/multipliers for arbitrary frequency synthesis - only spread-spectrum depth and output enables are configurable via I²C.

What is the role of the IREF pin and how is it used in layout?

IREF is an analog current reference input requiring a precision 12.4-kΩ resistor to ground. This sets the internal bias current for all clock buffers and PLLs. Layout best practice: place the resistor within 5 mm of IREF, use short traces, avoid routing near noisy digital lines, and connect to clean analog ground (VSSA) - not shared digital ground - to maintain jitter performance below 15 ps RMS.