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Home > Products > Integrated Circuits (ICs) > Embedded > CPLDs (Complex Programmable Logic Devices)

Infineon Technologies CY37128P160-167AXC

Name: CY37128P160-167AXC
Brand: Infineon Technologies
SKU: CY37128P160-167AXC
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: CY37128P160-167AXC

Manufacturer:: Infineon Technologies

Category:: CPLDs (Complex Programmable Logic Devices)

Package:: 160-LQFP

Datasheet:: CY37128P160-167AXC.pdf

Description:: IC CPLD 128MC 6.5NS 160TQFP

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Product details

Overview

CY37128P160-167AXC from Cypress Semiconductor is a 128-macrocell In-System Reprogrammable (ISR™) Complex Programmable Logic Device (CPLD) in the Ultra37000 family, operating at 5V with 160-pin TQFP packaging. It delivers 167 MHz maximum frequency (f_MAX) and 6.5 ns propagation delay (t_PD), supports up to 128 I/O pins, features four synchronous clocks per logic block, and implements JTAG-based reconfiguration without pinout or timing changes - used in PCI-compliant interface glue logic and legacy system upgrades.

For engineers reviewing the CY37128P160-167AXC datasheet, CY37128P160-167AXC pinout, CY37128P160-167AXC application, or CY37128P160-167AXC equivalent, key selection criteria include macrocell count, I/O pin count, t_PD/f_MAX speed bin, VCCO voltage flexibility (3.3V/5V I/O), bus-hold programmability, and JTAG ISR support for field updates in industrial control and telecom backplane designs.

Technical Context

The CY37128P160-167AXC integrates eight logic blocks, each with a 72×87 product term array, 16 macrocells, and an intelligent product term allocator supporting 0–16 product terms per macrocell. Its Programmable Interconnect Matrix (PIM) provides 36 global inputs per logic block with no route-dependent delays - all PIM timing incorporated into guaranteed t_PD and f_MAX specs.

Each logic block accepts four dedicated synchronous clocks (CLK0–CLK3) plus one asynchronous product term clock (PTCLK), with polarity control per clock. All 128 I/Os support programmable bus-hold and slew-rate control (fast/slow), and five dedicated input pins include four clock-capable inputs - enabling mixed-edge, multi-clock domain logic synthesis without external timing compensation.

Key Specifications

Parameter	Value and Actual Design Meaning
Macrocells	128 total - defines maximum combinational or registered logic capacity per device
Maximum Frequency (f_MAX)	167 MHz - guarantees synchronous operation up to this clock rate under worst-case conditions
Propagation Delay (t_PD)	6.5 ns - worst-case path delay from input to registered output, independent of fanout or PIM routing
I/O Pins	128 user-programmable - supports high-pin-count interface bridging with configurable drive strength
Supply Voltage (V_CC)	5.0 V ± 10% - required for core logic and ISR programming; V_CCO pins support 3.3V or 5V I/O levels
Package	160-pin TQFP - surface-mount, 24×24 mm body, 0.5 mm pitch, RoHS-compliant lead-free option available
JTAG Interface	IEEE 1149.1-compliant - enables in-system reprogramming, boundary scan testing, and debug without device removal

Pinout & Package

Package: 160-pin Thin Quad Flat Package (TQFP), 24 mm × 24 mm body, 0.5 mm lead pitch, exposed thermal pad (non-electrical), JEDEC MO-159AC compliant.

Pin/Terminal	Circuit Role	Design Meaning
TCK, TMS, TDI, TDO	JTAG Test Access Port	Serial interface for ISR programming, boundary scan, and device configuration; requires pull-up on TMS
CLK0–CLK3	Dedicated Clock Inputs	Four globally distributed synchronous clocks; each configurable for rising/falling edge triggering per logic block
V_CC, GND	Power Supply	Core logic supply (5V); 12 V_CC and 12 GND pins ensure low-noise power delivery across high-speed switching
V_CCO	I/O Output Voltage Reference	Separate 3.3V or 5V supply per bank; sets output voltage level and determines 5V-tolerance behavior
I/O[0]–I/O[127]	Programmable Bidirectional I/O	Configurable as input, output, or bidirectional with bus-hold, slew control, and Schmitt-trigger options
OE[0]–OE[3]	Output Enable Product Terms	Four dedicated OE product terms - each controls up to eight macrocells, enabling fine-grained tri-state management

Key Features

Feature	Design Value
In-System Reprogrammability (ISR™)	JTAG-based field updates without board rework - preserves pinout and timing across design iterations
Intelligent Product Term Allocator	Assigns 0–16 product terms per macrocell dynamically; enables optimal logic fitting without manual steering
Flexible Clocking Architecture	Four synchronous clocks + one product term clock per logic block, each with polarity control for mixed-edge timing
Programmable Bus-Hold	Weak latch on all I/Os eliminates need for external pull-ups - reduces BOM cost and improves noise immunity during bus float
PCI Compliance	Meets electrical and timing requirements of PCI Local Bus Specification Rev. 2.2 - validated for 33 MHz 5V signaling

Applications

Industrial PLC Backplane Interface

Legacy System Bus Translation

Use Scenario: Bridging between ISA and PCI buses in programmable logic controller chassis where protocol timing must be deterministic and field-upgradable.

IC Role / Device Role / Timing Role: Glue logic CPLD implementing address decoding, bus arbitration, and handshaking with fixed 6.5 ns t_PD.

Use Value: Eliminates custom ASIC redesign; ISR allows firmware-driven logic updates during maintenance windows without hardware change.

Use Scenario: Replacing obsolete PAL/GAL devices in medical imaging equipment requiring long-term component availability and EOL mitigation.

IC Role / Device Role / Timing Role: Pin-compatible logic replacement with identical I/O mapping and guaranteed setup/hold margins.

Use Value: Maintains legacy PCB layout while adding JTAG debug visibility and 167 MHz timing headroom for future feature expansion.

Telecom Line Card Control

Automated Test Equipment (ATE) Pattern Generator

Use Scenario: Managing LED status indicators, relay drivers, and FPGA configuration sequencing on multi-port DSLAM line cards.

IC Role / Device Role / Timing Role: I/O expander and state machine controller with 128 programmable pins and bus-hold for unconnected test points.

Use Value: Reduces discrete logic count by >70%; programmable slew rate minimizes EMI during high-speed relay toggling.

Use Scenario: Generating synchronized stimulus waveforms for IC functional testing, requiring precise clock domain crossing and pattern memory addressing.

IC Role / Device Role / Timing Role: High-speed sequencer using product term clocks and macrocell registers to align test vectors across 32-bit data paths.

Use Value: Achieves sub-7 ns timing resolution without external delay lines; JTAG allows real-time waveform modification during test execution.

Equivalent & Alternatives

The following parts are listed as comparable options for similar CPLD-based interface logic applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AMD XC95144XL-10TQ144C	144 macrocells, 10 ns t_PD, 3.3V-only core, 144-pin TQFP - lacks V_CCO flexibility and 5V PCI compliance	Requires level-shifting for 5V bus interfaces; not drop-in for existing 5V designs using CY37128P160-167AXC	Select when migrating to 3.3V-only systems and prioritizing lower static power over PCI compatibility
Lattice ispMACH 4128V-10T144	128 macrocells, 10 ns t_PD, 3.3V core, 144-pin TQFP - supports IEEE 1532 ISP but no 5V I/O tolerance	Cannot directly replace in 5V environments; requires redesign of V_CCO and termination networks	Choose for new 3.3V designs needing higher density per pin and enhanced security fuse options

Compared with CY37128P160-167AXC, the AMD XC95144XL offers higher macrocell count but sacrifices 5V PCI compliance and V_CCO flexibility, while the Lattice ispMACH 4128V provides modern ISP but mandates full 3.3V system redesign - making CY37128P160-167AXC uniquely suited for brownfield 5V industrial upgrades.

Availability

CY37128P160-167AXC is available at Aetrix Electronics and suitable for industrial PLC backplane interface, legacy system bus translation, and telecom line card control requiring stable component supply across extended product lifecycles.

Supply support for CY37128P160-167AXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a U.S.-based semiconductor company specializing in programmable logic, memory, and USB/USB-C solutions, founded in 1982 and headquartered in San Jose, California.

The Ultra37000 CPLD family was designed to deliver high-density, pin-stable, in-system reprogrammable logic for industrial control, telecom infrastructure, and embedded system upgrades - emphasizing deterministic timing, PCI compliance, and long-term manufacturability.

FAQ

Is CY37128P160-167AXC compatible with 3.3V I/O signaling?

Yes - the device supports 3.3V I/O levels when V_CCO pins are connected to 3.3V, delivering JEDEC-compliant CMOS outputs that remain 5V-tolerant. Core logic operates at 5V, so V_CC must remain at 5V regardless of V_CCO setting. This dual-voltage capability enables seamless interfacing with both legacy 5V and modern 3.3V subsystems without level shifters.

Does CY37128P160-167AXC require external configuration memory?

No - it is non-volatile and retains its configuration without external memory. The device uses internal EEPROM cells to store logic configuration, enabling instant-on operation after power-up. Configuration is loaded automatically from on-chip memory; JTAG is used only for reprogramming, not boot loading.

Can CY37128P160-167AXC replace older CY37128-167AC parts?

Yes - CY37128P160-167AXC is a direct replacement for CY37128-167AC in 160-pin TQFP packages. The "P" suffix denotes plastic TQFP, "A" indicates commercial temperature range (0°C to 70°C), and "XC" confirms lead-free RoHS compliance. Pinout, timing, and JTAG functionality are identical; only package marking and environmental compliance differ.

What development tools support CY37128P160-167AXC?

Cypress Warp v6.0+ and third-party tools including Lattice ispLEVER Classic (with Cypress library add-on) fully support this device. Synthesis, fitting, and JTAG programming are validated for the Ultra37000 architecture. Boundary scan testing and in-circuit debugging via TAP controller are enabled out-of-box without additional license fees.

CY37128P160-167AXC Specifications

Product attributes: Attribute value

Manufacturer:: Infineon Technologies

Series:: Ultra37000™

Package/Case:: 160-LQFP

Packaging:: Tray

Product Status:: Obsolete

Programmable:: Not Verified

Programmable Type:: In-System Reprogrammable™ (ISR™) CMOS

Delay Time tpd(1) Max:: 6.5 ns

Voltage Supply - Internal:: 4.75V ~ 5.25V

Number of Logic Elements/Blocks:: -

Number of Macrocells:: 128

Number of Gates:: -

Number of I/O:: 133

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 160-TQFP (24x24)

CY37128P160-167AXC FAQ

1.How can I place an order for CY37128P160-167AXC through Aetrix?

Please submit a Request for Quotation (RFQ) for CY37128P160-167AXC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for CY37128P160-167AXC reliable?

The price and inventory of CY37128P160-167AXC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY37128P160-167AXC is usually 5 days.

3.What payment methods are accepted for CY37128P160-167AXC?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY37128P160-167AXC transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for CY37128P160-167AXC?

CY37128P160-167AXC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your CY37128P160-167AXC order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for CY37128P160-167AXC?

For technical support, including CY37128P160-167AXC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY37128P160-167AXC requirements.

6.How does Aetrix verify that CY37128P160-167AXC is sourced from the original manufacturer or authorized distributors?

All CY37128P160-167AXC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY37128P160-167AXC meets industry standards.

7.What is the process for return or replacement of CY37128P160-167AXC?

All CY37128P160-167AXC units undergo pre-shipment inspection (PSI). If there is an issue with CY37128P160-167AXC, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The CY37128P160-167AXC part is unused and in its original packaging.

Return procedure for CY37128P160-167AXC:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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