Infineon Technologies CY37128P84-100JXC

Overview

CY37128P84-100JXC from Cypress Semiconductor is a 128-macrocell In-System Reprogrammable (ISR™) Complex Programmable Logic Device (CPLD) in the Ultra37000 family, operating at 5V with 100 MHz maximum frequency (tPD = 10 ns), 84-pin PLCC package, and 69 I/O pins. It features four synchronous clocks, programmable bus-hold on all I/Os, and JTAG-based reconfiguration for pinout- and timing-stable design iterations in PCI-compliant embedded control systems.

For engineers reviewing the CY37128P84-100JXC datasheet, CY37128P84-100JXC pinout, CY37128P84-100JXC application, or CY37128P84-100JXC equivalent, key selection criteria include macrocell count, I/O pin count, tPD timing bin (10 ns), VCCO voltage flexibility (5V/3.3V interface support), and JTAG ISR capability for field-upgradable logic in industrial control and communications hardware.

Technical Context

The CY37128P84-100JXC implements a modular architecture with two logic blocks, each containing a 72×87 product term array, intelligent product term allocator (0–16 terms per macrocell), and 16 macrocells (mix of I/O and buried). Its Programmable Interconnect Matrix (PIM) delivers 36 global inputs per logic block with no route-dependent delays.

It supports flexible clocking via four dedicated synchronous clocks (CLK0–CLK3) plus one asynchronous product-term clock (PTCLK), all with programmable polarity; all I/Os feature configurable slew rate (fast/slow) and bus-hold latching to maintain signal state during high-impedance conditions without external pull-ups.

Key Specifications

Pinout & Package

Package: 84-pin Plastic Leaded Chip Carrier (PLCC), 27.94 mm × 27.94 mm, JEDEC MS-026AC standard, lead (Pb)-free option available.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CPLD-based glue logic and interface applications.

Compared with XC95144XL-10TQ100I and ATF1502AS-10JU84, CY37128P84-100JXC uniquely combines 5V core operation, dual-voltage VCCO, on-chip bus-hold, and ISR stability-making it optimal for maintaining legacy system compatibility while enabling field-upgradable logic in constrained PLCC layouts.

Availability

CY37128P84-100JXC is available at Aetrix Electronics and suitable for industrial PLC expansion, PCI interface design, and legacy system emulation requiring stable component supply, long-lifecycle support, and verified JTAG reprogrammability.

Supply support for CY37128P84-100JXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a U.S.-based semiconductor company specializing in programmable logic, memory, and USB/USB-C solutions for industrial, automotive, and communications markets.

The Ultra37000 CPLD family was designed to deliver high-density, pinout-stable, in-system reprogrammable logic for mission-critical embedded control and interface applications where design iteration and long-term supply assurance are essential.

FAQ

What voltage levels does CY37128P84-100JXC support on its I/O pins?

CY37128P84-100JXC supports both 3.3V and 5V I/O signaling via separate VCCO pins. When VCCO is tied to 3.3V, outputs meet JEDEC 3.3V CMOS levels and remain 5V-tolerant; when tied to 5V, outputs deliver standard 5V TTL levels. Core VCC must be 5V.

Does CY37128P84-100JXC require external pull-up resistors on unused I/O pins?

No. All I/O pins feature user-programmable bus-hold circuitry-a weak on-chip latch that maintains the last driven logic state during high-impedance conditions. This eliminates the need for external pull-ups and reduces board space and noise in bus-interface applications.

Can CY37128P84-100JXC be reprogrammed in the system without disrupting connected logic?

Yes. Its JTAG-compliant ISR™ capability allows full in-system reprogramming via TDI/TDO pins while powered and mounted on the board. Design changes retain identical pinout and timing behavior-no PCB or firmware timing adjustments are needed after update.

How many clock sources are available for macrocell registers in CY37128P84-100JXC?

CY37128P84-100JXC provides five clock sources per logic block: four global synchronous clocks (CLK0–CLK3), each with programmable polarity, plus one asynchronous product-term clock (PTCLK) derived from local logic. All clocks are independently assignable to any macrocell register.