Infineon Technologies CY7B9920-5SC
- Part No.:
- CY7B9920-5SC
- Manufacturer:
- Infineon Technologies
- Package:
- 24-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
CY7B9920-5SC.pdf
- Description:
- IC FANOUT BUFFER 24SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,560
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Product details
Overview
CY7B9920-5SC from Cypress Semiconductor is a CMOS-output, low-skew clock buffer with integrated PLL, delivering zero input-to-output delay and <250 ps max output skew across eight outputs. It operates from 15 MHz to 80 MHz (FS pin-selectable), drives 50Ω terminated lines, and maintains 50% duty cycle - deployed in Pentium™-based computing systems for synchronized clock distribution.
For engineers reviewing the CY7B9920-5SC datasheet, CY7B9920-5SC pinout, CY7B9920-5SC application, or CY7B9920-5SC equivalent, key selection criteria include output skew tolerance (<250 ps), CMOS-level drive capability (VCC/2 thresholds), FS-selectable frequency range (15–80 MHz), and PLL lock time (≤0.5 ms) under industrial temperature conditions.
Technical Context
The CY7B9920-5SC implements a fully integrated phase-locked loop with voltage-controlled oscillator (VCO), phase/frequency detector, and filter - enabling zero-delay clock forwarding. Its three-level FS pin selects VCO operating bands (LOW/MID/HIGH), directly determining nominal output frequencies of 15–30 MHz, 25–50 MHz, or 40–80 MHz.
All eight Q[0..7] outputs are CMOS-compatible (VOH = VCC–0.75 V, VOL = 0.45 V @ IOL = 46 mA), driven from dedicated VCCN supply pins, while internal logic runs on separate VCCQ. The device supports direct REF-to-output bypass in TEST mode, decoupling the PLL for deterministic timing validation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Skew (tSKEW) | <250 ps max - ensures simultaneous edge alignment across all 8 outputs driving 50Ω loads |
| Operating Frequency | 15–80 MHz (FS-selectable) - supports scalable clock tree design without external dividers |
| Jitter (RMS) | 25 ps RMS - meets tight timing margin requirements in high-speed CPU and memory interfaces |
| Duty Cycle Variation | ±1.2 ns max - preserves 50% duty cycle integrity critical for DDR and double-data-rate signaling |
| Propagation Delay (tPD) | –0.7 to +0.7 ns (REF rise to FB rise) - enables precise feedback path timing calibration |
| PLL Lock Time | 0.5 ms - guarantees rapid synchronization after frequency change or power-up |
| Supply Separation | VCCN (output drivers) and VCCQ (internal logic) - isolates noise-sensitive PLL from switching transients |
Pinout & Package
24-pin SOIC (S13, 300-mil) package with exposed thermal pad not present; lead finish is matte tin, RoHS-compliant per legacy spec.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| REF | Input | Reference clock source for PLL; must meet 5 ns min pulse width (HIGH/LOW) |
| FB | Input | Feedback signal tied to one Q output; closes PLL loop for zero-delay operation |
| FS | Input | Three-level frequency select (LOW/MID/HIGH); sets VCO operating band and max fNOM |
| TEST | Input | Three-level control; LOW = normal PLL mode, MID/HIGH = PLL bypass for direct REF routing |
| Q0–Q7 | Output | Eight CMOS clock outputs; each independently drives 50Ω-terminated transmission lines |
| VCCN | Power | 5V ±10% supply for output buffers only; separate from VCCQ to reduce crosstalk |
| VCCQ | Power | 5V ±10% supply for internal PLL and logic; decoupled from VCCN for jitter suppression |
| GND | Power | Common ground reference for both power domains and signal IO |
Key Features
| Feature | Design Value |
|---|---|
| Zero Input-to-Output Delay | PLL-based architecture aligns REF edge with Q outputs within ±0.7 ns, eliminating fixed latency |
| Sub-250 ps Output Skew | Guaranteed skew across all 8 outputs under 50Ω load ensures synchronous sampling in multi-lane systems |
| FS-Selectable Frequency Range | Hardware-configurable VCO bands (15–30 / 25–50 / 40–80 MHz) enable single BOM for multiple clock speeds |
| CMOS Output Drive | Full-swing outputs compliant with VCC/2 thresholds support 3.3V and 5V logic families without level shifters |
| Dedicated Power Domains | Separated VCCN (drivers) and VCCQ (PLL/logic) suppress supply-induced jitter and improve PSRR |
Applications
| Desktop CPU Clock Distribution | Pentium™-Based Motherboard Timing |
|---|---|
|
Use Scenario: Distributing synchronized 66 MHz system clock to CPU, cache controller, and chipset on ATX motherboards. IC Role / Device Role / Timing Role: Zero-delay clock buffer with PLL feedback to eliminate inter-chip skew between processor and northbridge. Use Value: Enables reliable 66 MHz front-side bus operation by maintaining <250 ps skew across 8 loads, meeting Intel's P54C timing spec. |
Use Scenario: Generating matched clock phases for dual-bank SDRAM and PCI bus arbitration logic. IC Role / Device Role / Timing Role: Eight-output CMOS clock driver with independent 50Ω termination per line, reducing stub reflections. Use Value: Eliminates need for discrete resistive termination networks, saving PCB area and improving signal integrity at 50–80 MHz. |
| Industrial Control Backplane Clocking | Legacy Embedded Computing Systems |
|
Use Scenario: Providing deterministic clock signals across modular I/O cards in DIN-rail mounted PLC chassis. IC Role / Device Role / Timing Role: Industrial-grade (–40°C to +85°C) clock repeater with 0.5 ms PLL lock for hot-swap reconfiguration. Use Value: Guarantees sub-millisecond resynchronization after card insertion, preventing firmware hang during field maintenance. |
Use Scenario: Replacing aging discrete clock trees in medical imaging controllers requiring long-term component availability. IC Role / Device Role / Timing Role: Pin-compatible upgrade path from CY7B9920–5SI with documented lifecycle continuity and same SOIC footprint. Use Value: Maintains legacy board layout while upgrading from TTL (CY7B9910) to CMOS drive strength and lower jitter. |
Equivalent & Alternatives
CY7B9920-5SC has two verified drop-in alternatives with documented electrical and functional differences.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CY7B9920-5SI | Same silicon, industrial temperature grade (–40°C to +85°C) vs. commercial (0°C to +70°C); identical AC/DC specs | Required for extended-temperature deployments; no PCB or firmware changes needed | Select when operating ambient exceeds 70°C or requires MIL-STD-810 thermal cycling compliance |
| CY7B9920-7SC | Relaxed skew spec (750 ps max vs. 250 ps); otherwise identical pinout, timing, and drive strength | Suitable for non-critical clock domains where cost reduction outweighs tight skew requirements | Choose for cost-sensitive applications with >500 ps skew tolerance, e.g., peripheral bus clocks |
Compared with CY7B9920-5SI, the -5SC offers lower temperature qualification cost but reduced thermal margin; versus CY7B9920-7SC, it delivers 3× tighter skew control essential for CPU clock trees - making it the optimal choice for performance-critical computing timing.
Availability
CY7B9920-5SC is available at Aetrix Electronics and suitable for desktop motherboard design, industrial PLC backplanes, legacy embedded computing upgrades, and Pentium™-based system refurbishment requiring stable component supply over extended production lifecycles.
Supply support for CY7B9920-5SC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Cypress Semiconductor Corporation, now part of Infineon Technologies, designed high-performance timing, memory, and programmable logic devices for computing and industrial markets from 1982 until its 2020 acquisition.
CY7B9920 belongs to Cypress's low-skew clock buffer product line, engineered specifically for synchronized clock distribution in Pentium-class systems where deterministic delay and minimal inter-output skew were critical for FSB and memory interface timing.
FAQ
What is the maximum capacitive load the CY7B9920-5SC can drive per output?
The CY7B9920-5SC is characterized for 30 pF load in –2 and –5 speed grades, and 50 pF in –7 grade. Driving beyond 30 pF at 80 MHz may degrade tORISE/tOFALL and increase jitter; Cypress specifies timing only up to 30 pF for CY7B9920-5SC. External series termination remains mandatory for 50Ω line matching regardless of capacitive load.
Can the FS pin be left unconnected?
Yes - the FS pin has internal termination holding unconnected inputs at VCC/2, which corresponds to MID state (25–50 MHz range). However, Cypress warns that switching FS mid-operation may cause PLL unlock and output glitches; it must be set at power-up and held static during normal operation.
Is the CY7B9920-5SC compatible with 3.3V-only systems?
No - the device requires 5V ±10% on both VCCN and VCCQ; it does not support 3.3V core or I/O operation. Its CMOS outputs swing rail-to-rail (0.45 V to VCC–0.75 V), so interfacing with 3.3V logic requires external level translation or series resistor matching to avoid overvoltage damage.
Does the CY7B9920-5SC provide short-circuit protection on its outputs?
No - the datasheet explicitly states "CY7B9920 outputs are not short circuit protected." Absolute maximum rating for output short-circuit current is –250 mA (tested one output at a time, <1 second, <10% duty cycle), but sustained shorts will exceed thermal limits and cause permanent failure.
CY7B9920-5SC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Series:
- -
- Package/Case:
- 24-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Fanout Buffer (Distribution), Zero Delay Buffer
- PLL:
- Yes
- Input:
- Clock
- Output:
- CMOS
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:8
- Differential - Input:Output:
- No/No
- Frequency - Max:
- 80MHz
- Divider/Multiplier:
- No/No
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-SOIC
CY7B9920-5SC FAQ
1.How can I place an order for CY7B9920-5SC through Aetrix?
Please submit a Request for Quotation (RFQ) for CY7B9920-5SC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY7B9920-5SC reliable?
The price and inventory of CY7B9920-5SC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY7B9920-5SC is usually 5 days.
3.What payment methods are accepted for CY7B9920-5SC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY7B9920-5SC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY7B9920-5SC?
CY7B9920-5SC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY7B9920-5SC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY7B9920-5SC?
For technical support, including CY7B9920-5SC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY7B9920-5SC requirements.
6.How does Aetrix verify that CY7B9920-5SC is sourced from the original manufacturer or authorized distributors?
All CY7B9920-5SC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY7B9920-5SC meets industry standards.
7.What is the process for return or replacement of CY7B9920-5SC?
All CY7B9920-5SC units undergo pre-shipment inspection (PSI). If there is an issue with CY7B9920-5SC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY7B9920-5SC part is unused and in its original packaging.
Return procedure for CY7B9920-5SC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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