Infineon Technologies CY7C1325G-133AXCT

Overview

CY7C1325G-133AXCT from Cypress Semiconductor is a 4-Mbit (256K × 18) synchronous flow-through SRAM with 133 MHz clock rate, 6.5 ns clock-to-output delay, 3.3 V core supply (VDD), and dual-voltage I/O (2.5 V/3.3 V VDDQ), designed for high-speed secondary cache interfacing in Pentium-class microprocessor systems.

For engineers reviewing the CY7C1325G-133AXCT datasheet, CY7C1325G-133AXCT pinout, CY7C1325G-133AXCT application, or CY7C1325G-133AXCT equivalent, key selection factors include burst mode control (MODE pin), asynchronous ZZ sleep enable, synchronous self-timed write architecture, and support for both ADSP/ADSC address strobes in cache controller designs.

Technical Context

The device implements a 2-bit on-chip wraparound burst counter fed by A[1:0], enabling Intel Pentium-compatible interleaved or linear burst sequences selected via the static MODE pin. All synchronous inputs - including addresses, CE1/CE2/CE3, ADSP/ADSC/ADV, BW[A:B], BWE, GW, and CLK - are registered on the positive clock edge.

Asynchronous controls include OE (output enable) and ZZ (sleep mode), with ZZ requiring external grounding per errata. The memory uses common I/O architecture with DQA/DQB/DQPA/DQPB bidirectional data buses, JEDEC JESD8-5-compliant signaling, and synchronous self-timed write logic eliminating external write pulse timing constraints.

Key Specifications

Pinout & Package

Package: 100-pin TQFP (14 × 20 × 1.4 mm), Pb-free, RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous cache SRAM applications.

Compared with IS61LV25618AL-133TQLI and MT55L25618A-133:G, the CY7C1325G-133AXCT uniquely combines MODE-selectable burst sequencing, asynchronous ZZ sleep, and dual-voltage I/O - making it the only option among the three that satisfies Pentium-compatible cache timing, low-power idle states, and mixed-voltage system integration simultaneously.

Availability

CY7C1325G-133AXCT is available at Aetrix Electronics and suitable for Intel Pentium cache subsystems, embedded RISC processor caches, network packet buffers, and industrial motion controller memory requiring stable component supply and long-lifecycle support.

Supply support for CY7C1325G-133AXCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a U.S.-based semiconductor company specializing in high-performance memory, PSoC programmable systems-on-chip, and USB/USB-C solutions.

The CY7C1325G belongs to Cypress's legacy synchronous SRAM product line, engineered specifically for high-speed CPU cache applications requiring flow-through timing, burst flexibility, and low-latency deterministic access in x86 and embedded computing platforms.

FAQ

What is the correct configuration for the ZZ pin on CY7C1325G-133AXCT?

The ZZ pin (Pin 64) must be externally connected to ground per documented errata on page 21 of Rev. *R datasheet. Although described as an active-HIGH sleep input, leaving it floating or pulling it HIGH causes unreliable operation. Internal pull-down ensures safe default behavior only when externally grounded.

Does CY7C1325G-133AXCT support true 133 MHz operation with 6.5 ns access time?

Yes - the 6.5 ns clock-to-output delay (tCDV) is specified at 133 MHz under VDD = 3.3 V ± 0.3 V, VDDQ = 2.5 V or 3.3 V, TA = 0 °C to +70 °C, and CL = 30 pF. This value is measured from CLK rising edge to valid DQ output and is guaranteed across the commercial temperature range.

How does burst addressing work when MODE is tied to VDD versus GND?

When MODE = VDD or floating, the device executes interleaved burst order (0→2→4→6→1→3→5→7), matching Intel Pentium requirements. When MODE = GND, it executes linear burst order (0→1→2→3→4→5→6→7). The burst counter is always fed by A[1:0] and wraps after four addresses in both modes.

Can CY7C1325G-133AXCT operate with only 2.5 V on VDDQ while using 3.3 V on VDD?

Yes - VDD (core) and VDDQ (I/O) are independently powered. The device is fully compliant with JEDEC JESD8-5 for mixed-voltage operation: VDD = 3.3 V ± 0.3 V and VDDQ = 2.5 V ± 0.2 V may be used simultaneously, enabling direct interface to 2.5 V processors while maintaining 3.3 V internal logic integrity.