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Infineon Technologies CY7C1338G-117AXC
- Part No.:
- CY7C1338G-117AXC
- Manufacturer:
- Infineon Technologies
- Category:
- Memory
- Package:
- 100-LQFP
- Datasheet:
-
CY7C1338G-117AXC.pdf
- Description:
- IC SRAM 4MBIT PAR 117MHZ 100TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:4,233
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Product details
Overview
CY7C1338G-117AXC from Cypress Semiconductor is a 4-Mbit (128K × 32) synchronous flow-through SRAM with 117 MHz clock operation, 7.5 ns clock-to-output access time, 3.3 V core supply (VDD), 2.5/3.3 V I/O supply (VDDQ), and 100-pin TQFP package. It serves as a secondary cache RAM for high-speed microprocessors including Intel Pentium® and i486™, supporting both interleaved and linear burst sequences via MODE pin selection.
For engineers reviewing the CY7C1338G-117AXC datasheet, CY7C1338G-117AXC pinout, CY7C1338G-117AXC application, or CY7C1338G-117AXC equivalent, key selection criteria include synchronous burst timing control (ADSP/ADSC/ADV), byte-write granularity (BWA–BWD + BWE), global write capability (GW), asynchronous output enable (OE), and ZZ sleep mode entry/exit timing.
Technical Context
The CY7C1338G-117AXC implements a 2-bit on-chip wraparound burst counter fed by A[1:0], enabling four-word burst reads/writes with user-selectable linear or interleaved order determined by the static MODE pin. All address, data, and control inputs (except OE and ZZ) are registered on the rising edge of CLK.
It supports dual-address-strobe initiation (ADSP for processor-initiated, ADSC for controller-initiated bursts), synchronous self-timed writes, and asynchronous tri-state control via OE. The device operates with three synchronized chip enables (CE1 active-low, CE2 active-high, CE3 active-low) and includes dedicated byte-write registers per DQA–DQD byte lane.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 4 Mbit (128K × 32) - provides full-word cache line storage for 32-bit processors without external data bus widening. |
| Access Time (tCDV) | 7.5 ns at 117 MHz - defines maximum delay from CLK rise to valid DQ output during read cycles. |
| Core Supply (VDD) | 3.3 V ±5% - powers internal logic and memory array; requires tight regulation for timing stability. |
| I/O Supply (VDDQ) | 2.5 V or 3.3 V - independently configurable to match host processor I/O voltage, enabling mixed-voltage system interfacing. |
| Burst Mode Control | MODE pin strapping - LOW = linear burst (00→01→10→11); HIGH/floating = interleaved (00→01→10→11 → 01→00→11→10), matching Pentium® protocol. |
| Sleep Mode Entry | Asynchronous ZZ HIGH - reduces standby current to 40 mA while preserving data; requires 2 clock cycles to enter/exit. |
| Write Architecture | Synchronous self-timed write with GW override - eliminates external write pulse timing constraints; GW forces full 32-bit write regardless of BW[A:D] state. |
Pinout & Package
Package: 100-pin Thin Quad Flat Package (TQFP), lead-free, JEDEC-standard footprint with exposed thermal pad (not electrically connected).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK | Synchronous clock input | Rising-edge-triggered master timing reference for all registered inputs (address, control, data) and burst counter increment. |
| ADSP / ADSC | Address strobe inputs | ADSP initiates processor-originated bursts; ADSC initiates controller-originated bursts; ADSP takes priority when both asserted. |
| ADV | Burst address advance | Samples on CLK rise to increment internal 2-bit counter and generate next burst address automatically. |
| CE1, CE2, CE3 | Chip enable inputs | Three-level decode: CE1 (active-low), CE2 (active-high), CE3 (active-low); all must be active for device selection. |
| OE | Asynchronous output enable | Active-low; controls DQ direction asynchronously-LOW enables outputs, HIGH places DQs in high-impedance state. |
| ZZ | Asynchronous sleep control | Active-high; forces low-power snooze mode with guaranteed data retention; requires 2tCYC recovery before next access. |
| MODE | Burst sequence selector | Static strap pin: GND = linear burst; VDD/floating = interleaved burst; must remain stable during operation. |
| BWA–BWD, BWE | Byte write controls | BWA–BWD select DQA–DQD lanes; BWE enables byte write-both required for partial-word writes. |
| GW | Global write enable | Active-low synchronous override: forces full 32-bit write regardless of BW[A:D] states, simplifying burst write logic. |
| DQA–DQD | Common I/O data bus | Four 8-bit bidirectional lanes (32-bit total); direction controlled by OE; tri-stated automatically during writes for safety. |
Key Features
| Feature | Design Value |
|---|---|
| Flow-through synchronous architecture | Eliminates pipeline stalls in burst reads: data appears on DQs one clock after ADSP/ADSC assertion, with no additional wait states. |
| User-selectable burst order | Hardware-mode selection (MODE pin) enables drop-in compatibility with both Pentium®-interleaved and generic linear-burst systems. |
| Synchronous self-timed write | Internal write timing control removes dependency on external write pulse width or setup/hold margins, reducing PCB routing complexity. |
| Dual address strobe support | Separate ADSP and ADSC inputs allow clean separation between CPU-initiated and cache-controller-initiated memory transactions. |
| Flexible I/O voltage operation | VDDQ supports 2.5 V or 3.3 V, enabling direct interface to either generation of 32-bit microprocessors without level-shifting circuitry. |
Applications
| Intel Pentium®-Based Cache Subsystem | Embedded RISC Processor L2 Cache |
|---|---|
|
Use Scenario: Secondary cache buffer between Pentium® P54C/P55C CPU and main memory in desktop/workstation motherboards. IC Role / Device Role / Timing Role: Synchronous flow-through SRAM providing 32-bit burst reads with interleaved addressing aligned to Pentium® 2-1-1-1 access pattern. Use Value: Achieves 117 MHz sustained bandwidth (374 MB/s) with zero-wait-state burst transfers, eliminating glue logic for address sequencing. |
Use Scenario: On-board L2 cache for PowerPC 603/604 or MIPS R4000-class embedded controllers in telecom line cards. IC Role / Device Role / Timing Role: High-speed common-I/O SRAM implementing linear-burst cache lines under deterministic real-time OS scheduling. Use Value: Enables deterministic 7.5 ns read latency and synchronous write completion within fixed instruction cycles for hard real-time response. |
| Industrial Motion Controller Buffer | Network Packet Buffer |
|
Use Scenario: Position command buffering and interpolation data staging in multi-axis CNC motion controllers. IC Role / Device Role / Timing Role: Burst-capable SRAM storing segmented trajectory data with precise clock-aligned read/write timing for servo loop synchronization. Use Value: Supports jitter-free 117 MHz burst streaming to FPGA-based motion sequencers, maintaining sub-microsecond timing alignment across axes. |
Use Scenario: Temporary packet storage in 10/100 Mbps Ethernet switch ASICs handling cut-through forwarding. IC Role / Device Role / Timing Role: Low-latency, flow-through SRAM acting as ingress/egress FIFO with synchronous burst fill and drain operations. Use Value: Delivers 7.5 ns read access and 2-cycle ZZ sleep entry/exit, enabling dynamic power gating during packet idle periods without data loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous burst SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IS61LV12832AL-117T | 128K × 32, 3.3 V only VDD/VDDQ, no ZZ sleep, no MODE-selectable burst, 100-pin TQFP. | Lacks burst mode flexibility and low-power sleep; suitable only for fixed-linear-burst systems without power gating needs. | Select when burst order is fixed and system-level power management is handled externally. |
| MT55L212832A-117:G | 128K × 32, 3.3 V core/I/O, no ADSP/ADSC dual strobe, no MODE pin, 119-ball BGA only. | Requires redesign for single-strobe interface and BGA layout; lacks hardware burst-order selection and TQFP option. | Select only if board redesign to BGA and simplified control interface is acceptable. |
Compared with IS61LV12832AL-117T and MT55L212832A-117:G, the CY7C1338G-117AXC uniquely delivers hardware-configurable burst order, asynchronous sleep control (ZZ), and dual-address-strobe support in a pin-compatible 100-pin TQFP package-critical for legacy Pentium®-based designs and power-constrained embedded caches.
Availability
CY7C1338G-117AXC is available at Aetrix Electronics and suitable for Intel Pentium®-based motherboard designs, industrial motion controller buffers, and network packet buffering applications requiring stable component supply, long-lifecycle support, and verified pinout compatibility.
Supply support for CY7C1338G-117AXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Cypress Semiconductor (now part of Infineon Technologies) is a U.S.-based semiconductor company specializing in high-performance memory, microcontrollers, and programmable logic solutions for computing and industrial markets.
The CY7C1338G belongs to Cypress's synchronous SRAM product line, engineered specifically for secondary cache applications in x86 and RISC microprocessor systems requiring deterministic burst timing, low-latency flow-through access, and flexible voltage/interface support.
FAQ
What is the function of the MODE pin on CY7C1338G-117AXC?
The MODE pin selects burst address sequence behavior: tied LOW (GND) enables linear burst order (00→01→10→11); tied HIGH (VDD) or left floating enables interleaved burst order (00→01→10→11→01→00→11→10), matching Intel Pentium® protocol. It is a static strap pin and must not change during operation.
How does the ZZ pin affect power consumption and timing?
Asserting ZZ HIGH places the device in snooze mode, reducing standby current to 40 mA while preserving data integrity. Entry and exit each require exactly two clock cycles (2tCYC); during this window, CE1/CE2/CE3, ADSP, and ADSC must remain inactive to ensure reliable recovery.
Can CY7C1338G-117AXC operate with 2.5 V I/O while using 3.3 V core supply?
Yes. VDD is fixed at 3.3 V ±5% for core logic and memory array, while VDDQ may be independently set to either 2.5 V or 3.3 V to match the host processor's I/O voltage domain-enabling seamless integration into mixed-voltage systems without external level shifters.
What distinguishes ADSP from ADSC in burst initiation?
ADSP (Address Strobe Processor) initiates bursts originating from the CPU; ADSC (Address Strobe Controller) initiates bursts from a cache controller or DMA engine. ADSP has priority-if both are asserted simultaneously, only ADSP is recognized. Both sample addresses on CLK rise and load A[1:0] into the burst counter.
CY7C1338G-117AXC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Series:
- -
- Package/Case:
- 100-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Synchronous, SDR
- Memory Size:
- 4Mbit
- Memory Organization:
- 128K x 32
- Memory Interface:
- Parallel
- Clock Frequency:
- 117 MHz
- Write Cycle Time - Word, Page:
- -
- Access Time:
- 7.5 ns
- Voltage - Supply:
- 3.15V ~ 3.6V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 100-TQFP (14x20)
CY7C1338G-117AXC FAQ
1.How can I place an order for CY7C1338G-117AXC through Aetrix?
Please submit a Request for Quotation (RFQ) for CY7C1338G-117AXC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY7C1338G-117AXC reliable?
The price and inventory of CY7C1338G-117AXC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY7C1338G-117AXC is usually 5 days.
3.What payment methods are accepted for CY7C1338G-117AXC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY7C1338G-117AXC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY7C1338G-117AXC?
CY7C1338G-117AXC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY7C1338G-117AXC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY7C1338G-117AXC?
For technical support, including CY7C1338G-117AXC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY7C1338G-117AXC requirements.
6.How does Aetrix verify that CY7C1338G-117AXC is sourced from the original manufacturer or authorized distributors?
All CY7C1338G-117AXC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY7C1338G-117AXC meets industry standards.
7.What is the process for return or replacement of CY7C1338G-117AXC?
All CY7C1338G-117AXC units undergo pre-shipment inspection (PSI). If there is an issue with CY7C1338G-117AXC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY7C1338G-117AXC part is unused and in its original packaging.
Return procedure for CY7C1338G-117AXC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CY7C1338G-117AXC Tags
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