Infineon Technologies CY7C1347F-133AC

Overview

CY7C1347F-133AC from Cypress Semiconductor is a 4-Mb (128K × 36) pipelined synchronous SRAM optimized for zero-wait-state secondary cache in high-performance computing systems. It operates with a 3.3V core supply, 2.5V/3.3V I/O tolerance, and delivers 4.0 ns clock-to-output access time at 133 MHz. Its fully registered inputs/outputs, dual address strobes (ADSP/ADSC), and user-selectable Intel Pentium®-compatible or linear burst mode enable seamless integration with CPU/cache controllers.

For engineers reviewing the CY7C1347F-133AC datasheet, CY7C1347F-133AC pinout, CY7C1347F-133AC application, or CY7C1347F-133AC equivalent, key selection criteria include burst sequence control via MODE pin, synchronous self-timed write architecture, ZZ sleep mode support, and compatibility with depth-expanded memory banks using CE1/CE2/CE3 bank selection.

Technical Context

The CY7C1347F-133AC implements a fully synchronous, pipelined architecture where all inputs-including address, byte write enables, and chip selects-are registered on the rising edge of CLK, and all outputs pass through output registers synchronized to the same edge. Its 2-bit wraparound burst counter captures A[1:0] at burst initiation and auto-increments per ADV assertion.

Burst sequencing is statically selected via the MODE pin (GND = linear, VDDQ/floating = interleaved), supporting both Intel Pentium® and PowerPC®-style cache protocols. Write operations are either ADSP-triggered (two-cycle) or ADSC-triggered (single-cycle), with synchronous self-timed internal write timing eliminating external write pulse generation.

Key Specifications

Pinout & Package

Package: 100-pin TQFP (JEDEC standard), body size 14 mm × 14 mm, 0.5 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous pipelined SRAM applications.

Compared with IS61LV12836A-133TQLI and MT55LSD12836D-133:J, the CY7C1347F-133AC uniquely supports 2.5V/3.3V I/O interoperability, asynchronous ZZ sleep, and dual-address-strobe cache control-critical for legacy Pentium®-compatible and low-power industrial systems.

Availability

CY7C1347F-133AC is available at Aetrix Electronics and suitable for secondary cache subsystems, high-speed network buffers, and real-time DSP data exchange requiring stable component supply across extended product lifecycles.

Supply support for CY7C1347F-133AC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a U.S.-based semiconductor company specializing in high-performance memory, microcontrollers, and programmable logic solutions for industrial, automotive, and communications markets.

The CY7C1347F belongs to Cypress's synchronous SRAM product line, engineered specifically for zero-wait-state CPU cache and high-bandwidth buffer applications demanding deterministic timing, burst flexibility, and low-latency I/O.

FAQ

What is the function of the MODE pin on CY7C1347F-133AC?

The MODE pin statically selects the burst sequence type: tied to GND for linear burst (e.g., PowerPC®), or to VDDQ/floating for Intel Pentium®-style interleaved burst. It is a strap pin-must remain static during operation and has an internal pull-up resistor. This selection determines how the 2-bit burst counter increments addresses during consecutive accesses.

How does the ZZ pin affect power consumption and timing?

The ZZ pin places the device in a low-power "sleep" mode when driven HIGH asynchronously. In this state, core current drops to ≤40 mA while retaining memory contents. Entry and exit each require two clock cycles, introducing a fixed 2-cycle latency penalty. During sleep, all outputs are three-stated and inputs are ignored except ZZ itself.

Can CY7C1347F-133AC operate with 2.5V I/O while using 3.3V core supply?

Yes. The device supports independent VDD = 3.3 V (core) and VDDQ = 2.5 V (I/O). When VDDQ = 2.5 V, all I/O pins are 3.3V-tolerant, allowing safe interfacing with 3.3V logic drivers. This dual-voltage capability enables migration from legacy 3.3V systems to lower-power 2.5V I/O domains without level-shifting.

What is the difference between ADSP and ADSC in burst operation?

ADSP (Address Strobe from Processor) and ADSC (Address Strobe from Controller) both initiate burst sequences but differ in priority and timing: ADSP is prioritized when both are asserted, and ADSP-triggered writes require two clock cycles, whereas ADSC-triggered writes complete in one cycle. This allows asymmetric control-e.g., CPU uses ADSP for cache fills, DMA controller uses ADSC for background transfers.