Infineon Technologies CY7C1347G-133AXCT

Overview

CY7C1347G-133AXCT from Infineon Technologies (formerly Cypress) is a 4-Mbit (128K × 36) pipelined synchronous SRAM optimized for zero-wait-state secondary cache in high-performance computing systems. It operates with a 3.3 V core supply (VDD), 2.5 V/3.3 V I/O supply (VDDQ), supports 133 MHz operation (4.0 ns max tCO), and features fully registered inputs/outputs, Intel Pentium–compatible interleaved or linear burst modes, and synchronous self-timed writes.

For engineers reviewing the CY7C1347G-133AXCT datasheet, CY7C1347G-133AXCT pinout, CY7C1347G-133AXCT application, or CY7C1347G-133AXCT equivalent, key selection criteria include burst mode flexibility (MODE pin), low-latency pipelined read timing (tCO = 4.0 ns), dual-voltage I/O tolerance, ZZ sleep mode support, and 100-pin TQFP packaging for memory subsystem integration.

Technical Context

The CY7C1347G-133AXCT implements a fully synchronous, clock-edge–triggered architecture: all address, control, and data inputs are registered on the rising CLK edge, and all outputs pass through output registers synchronized to the same edge. Its 2-bit wraparound burst counter captures A[1:0] at burst initiation and auto-increments for subsequent accesses within the 4-word burst.

Burst sequencing is statically selected via the MODE pin (GND = linear, VDDQ/floating = interleaved), and access initiation is dual-path-either ADSP (processor strobe) or ADSC (controller strobe)-with ADV controlling address advancement. Write operations use synchronous self-timed circuitry, eliminating external write pulse timing constraints.

Key Specifications

Pinout & Package

Supplied in a Pb-free 100-pin Thin Quad Flat Package (TQFP), 14 mm × 20 mm × 1.4 mm profile, with standard JEDEC footprint and thermal pad-compatible layout.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous burst SRAM applications.

Compared with AS7C34098B-133JCIN and IS61WV102436B-133TQLI, the CY7C1347G-133AXCT uniquely delivers Intel Pentium–interleaved burst capability, 2.5 V/3.3 V I/O flexibility, and hardware ZZ sleep-all in a single 100-pin TQFP package-making it optimal for legacy x86 cache upgrades and mixed-voltage embedded systems.

Availability

CY7C1347G-133AXCT is available at Aetrix Electronics and suitable for Intel Pentium–based cache subsystems, PowerPC L2 memory modules, multi-bank depth-expanded memory arrays, and real-time DSP data buffering requiring stable component supply and long-term industrial temperature support (–40°C to +85°C).

Supply support for CY7C1347G-133AXCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a global semiconductor leader headquartered in Munich, Germany, specializing in power systems, automotive ICs, and memory solutions, with broad industrial and automotive qualification expertise.

The CY7C1347G belongs to Infineon's legacy synchronous SRAM product line, originally developed by Cypress to address high-bandwidth, low-latency cache and buffering needs in performance-critical computing and communications infrastructure.

FAQ

What is the correct configuration for the ZZ pin on CY7C1347G-133AXCT?

The ZZ pin (Pin 64) must be externally connected to ground per documented errata (Page 22, Rev. *T). Although internally pulled down, grounding ensures reliable exit from sleep mode and prevents spurious entry during noise events. Leaving it floating or driving HIGH violates the erratum and may cause intermittent data retention failure.

Can CY7C1347G-133AXCT operate with VDDQ = 2.5 V while interfacing to a 3.3 V processor?

Yes - the I/O pins are 3.3 V tolerant when VDDQ = 2.5 V, allowing safe connection to 3.3 V processor buses without level shifters. This is explicitly specified in the Functional Description (Page 2) and Electrical Characteristics (Page 11), where V_IH(max) = 3.6 V and V_IL(min) = –0.5 V under 2.5 V VDDQ conditions.

How does burst addressing work when MODE = VDDQ versus MODE = GND?

When MODE = VDDQ (or floating), the device uses Intel Pentium–interleaved burst order: addresses advance as A, A+2, A+1, A+3. When MODE = GND, it uses linear order: A, A+1, A+2, A+3. The 2-bit burst counter loads A[1:0] at burst start and increments on each ADV assertion, wrapping automatically after four words.

Is CY7C1347G-133AXCT pin-compatible with faster speed grades like -250AXCT?

Yes - all speed grades (-133AXCT, -166AXCT, -200AXCT, -250AXCT) share identical 100-pin TQFP packaging, pinout, and DC/functional specifications. Only AC timing parameters (tCO, tCYC, tSU, tH) differ. System-level timing margining must account for the slower 4.0 ns tCO of the -133AXCT grade.