Infineon Technologies CY7C1355B-117AC

Overview

CY7C1355B-117AC from Cypress Semiconductor is a 9-Mbit synchronous flow-through SRAM (256K × 36 organization) with NoBL™ architecture, supporting 117-MHz zero-wait-state bus operation and 7.0 ns clock-to-output delay. It features registered inputs, byte-write capability, three chip enables for depth expansion, and operates with 3.3V/2.5V I/O supply - deployed in high-throughput packet buffering and network switch data path applications.

For engineers reviewing the CY7C1355B-117AC datasheet, CY7C1355B-117AC pinout, CY7C1355B-117AC application, or CY7C1355B-117AC equivalent, key selection criteria include burst order control (linear/interleaved), synchronous self-timed write timing, ZZ sleep mode power management, and TQFP-100 package compatibility with JEDEC-standard footprint.

Technical Context

The CY7C1355B-117AC implements a synchronous flow-through architecture where all address, control, and data inputs are registered on the rising edge of CLK, qualified by CEN. Its NoBL™ logic eliminates dead cycles between consecutive read/write operations, enabling true back-to-back transfers at 117 MHz.

Burst addressing is controlled by ADV/LD and MODE pins, supporting linear or interleaved sequences; byte write select (BWA–BWD) and WE jointly enable granular 8-bit writes. Output drivers are synchronously three-stated during write data phases to prevent bus contention, and OE remains asynchronous for flexible output control.

Key Specifications

Pinout & Package

Package: 100-lead Thin Quad Flat Package (TQFP), JEDEC standard MO-145AA, 14 mm × 14 mm body, 0.5 mm lead pitch, exposed thermal pad optional.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous burst SRAM applications.

Compared with IDT72V2115L10PF and IS61WV25636B, the CY7C1355B-117AC uniquely combines 117-MHz zero-wait operation, hardware-selectable burst order, and ZZ sleep - making it optimal for power-aware, burst-pattern-matched telecom and industrial control buffers.

Availability

CY7C1355B-117AC is available at Aetrix Electronics and suitable for network packet buffering, telecom line card memory, and industrial PLC data logging requiring stable component supply and long-term obsolescence management.

Supply support for CY7C1355B-117AC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a U.S.-based semiconductor company specializing in high-performance memory, microcontrollers, and programmable logic solutions for industrial, automotive, and communications markets.

The CY7C1355B belongs to Cypress's NoBL™ SRAM product line, engineered specifically for zero-latency, burst-oriented data buffering in networking infrastructure and real-time embedded systems.

FAQ

What is the function of the MODE pin on CY7C1355B-117AC?

The MODE pin is a static configuration input that determines burst sequence order: tied to GND for linear burst (0,1,2,3…), or to VDD/floating for interleaved burst (0,2,4,6…,1,3,5,7…). It is sampled at power-up and cannot be changed dynamically during operation. This setting must match the burst pattern expected by the controlling ASIC or FPGA.

Does CY7C1355B-117AC support asynchronous reads?

No - all read operations are strictly synchronous to CLK. Data output is registered and aligned to the rising edge of CLK, with t_CO = 7.0 ns specified at 117 MHz. OE is asynchronous but only controls output enable/disable state; it does not gate read data timing. The device has no true asynchronous access mode.

Can CE2 be used as an active-low enable like CE1 and CE3?

No - CE2 is defined as active HIGH per the datasheet and pin definition table. Using it as active LOW would violate timing and functional specifications. For three-way active-low decode, external inversion or logic is required; CE1 and CE3 remain the designated active-low enables for direct connection to address decoder outputs.

Is the ZZ pin required to be driven, or can it float?

ZZ may be left floating in normal operation, as its inactive state is LOW (sleep disabled). However, for robust ESD immunity and noise immunity in high-noise environments, Cypress recommends tying ZZ to VSS via a 10-kΩ pull-down resistor. Floating ZZ is acceptable but not best practice for industrial deployments.