Infineon Technologies CY7C63923-PVXC

Overview

CY7C63923-PVXC from Cypress Semiconductor is an enCoRe™ II 8-bit Flash-programmable microcontroller with integrated low-speed USB 2.0 and PS/2 interface, 48-pin SSOP package, 8 KB Flash, 256 bytes RAM, and internal 24 MHz oscillator ±1.5% accuracy. It serves as a peripheral controller in HID devices requiring dual-mode (USB/PS/2) operation without external crystals or pull-up resistors - e.g., optical mice and gaming controllers.

For engineers reviewing the CY7C63923-PVXC datasheet, CY7C63923-PVXC pinout, CY7C63923-PVXC application, or CY7C63923-PVXC equivalent, key selection criteria include its crystalless USB timing compliance, 36 GPIO with configurable 50-mA sink drive, dual-mode auto-configuration, integrated 3.3V regulator (125 mA), and capture timers for RF input edge timing in wireless peripherals.

Technical Context

The CY7C63923-PVXC implements a Harvard-architecture M8C CPU running up to 24 MHz, with USB Serial Interface Engine (SIE) supporting one device address, three endpoints (control + two data), and automatic D+/D– to PS/2 SCLK/SDATA reassignment. Its internal oscillator locks to USB traffic for ±1.5% timing accuracy without external crystal.

It integrates a 125-mA 3.3V regulator, programmable low-voltage detection, watchdog timer, and two 8-bit (or one 16-bit) capture timers tied to P0.5/TIO0 and P0.6/TIO1 - each storing independent rising/falling edge timestamps from the 16-bit free-running timer. GPIO ports 0–4 support maskable interrupts, open-drain outputs, and per-pin CMOS/TTL I/O configuration.

Key Specifications

Pinout & Package

Package: 48-pin SSOP (0.300" wide), RoHS-compliant, surface-mount. Thermal pad not present; standard JEDEC MS-013AC footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar low-speed USB peripheral controller applications.

Compared with CY7C63903-PC, the CY7C63923-PVXC offers 12 additional GPIO, Port 4 expansion, and identical capture timer functionality - critical for complex scanners or multi-function gamepads. Unlike CP2102N-A02-GM, it embeds full HID firmware execution, eliminating host dependency and enabling true standalone peripheral operation.

Availability

CY7C63923-PVXC is available at Aetrix Electronics and suitable for optical mouse development, gaming peripheral production, and industrial barcode scanner manufacturing requiring stable component supply across long-lifecycle programs.

Supply support for CY7C63923-PVXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a fabless semiconductor company specializing in USB, memory, PSoC, and programmable system-on-chip solutions for embedded applications.

The enCoRe™ II product line was designed specifically for cost-sensitive, low-speed USB HID peripherals - integrating oscillator, regulator, pull-ups, and dual-mode logic to minimize bill-of-materials and PCB complexity.

FAQ

Does CY7C63923-PVXC support full-speed USB?

No. The CY7C63923-PVXC supports only Low-Speed USB (1.5 Mbps) per USB 2.0 specification. It lacks the transceiver circuitry and timing precision required for Full-Speed (12 Mbps) operation. Its internal oscillator and SIE are optimized exclusively for LS-USB timing compliance and HID-class enumeration.

Can the internal 3.3V regulator power external USB PHYs or level shifters?

No. The 125-mA 3.3V regulator is intended for low-power peripheral circuitry such as sensors, LEDs, or logic buffers - not for powering external USB PHYs, which typically require higher current stability and tighter regulation. External USB PHYs must use dedicated regulators meeting USB electrical specifications.

How is PS/2 mode activated without external hardware?

PS/2 mode is activated automatically when the host initiates PS/2 handshaking on D+/D– lines (P1.0/P1.1). Firmware detects the PS/2 start condition via internal logic and reconfigures the pins as SCLK/SDATA with 5-kΩ internal pull-ups - no GPIO pin assignment, external resistors, or mode-select strapping is required.

What is the maximum achievable resolution of the capture timers?

The capture timers resolve edge events with 1-µs granularity, derived from the 16-bit free-running timer clocked at 1 MHz (1 µs period). Each 8-bit capture register stores a programmable 8-bit window of that timer - enabling precise measurement of pulse widths or intervals up to 255 µs per capture, extendable to 65.5 ms when ganged as 16-bit.