Infineon Technologies CY7C65620-56LTXC

Overview

CY7C65620-56LTXC from Cypress Semiconductor is a 2-port, single-transaction-translator (1TT) USB 2.0 hub controller supporting bus-powered operation, integrated 24 MHz PLL clock generation, and configurable SPI EEPROM-based device identification (VID/PID/DID). It integrates upstream 1.5 kΩ pull-up, downstream 15 kΩ pull-downs, and on-die termination resistors, targeting compact embedded hubs in monitor, docking station, and peripheral replicator systems.

For engineers reviewing the CY7C65620-56LTXC datasheet, CY7C65620-56LTXC pinout, CY7C65620-56LTXC application, or CY7C65620-56LTXC equivalent, key selection criteria include 2-port 1TT architecture, QFN-56 package compatibility with CY7C65640, bus-powered mode support, integrated USB transceivers, and SPI-configurable overcurrent detection polarity and port power switching behavior.

Technical Context

The CY7C65620 implements a USB 2.0 hub repeater for same-speed traffic (e.g., full-speed to full-speed) and a dedicated transaction translator (TT) for high-speed split transactions to full-/low-speed downstream devices. Its serial interface engine (SIE) handles bit stuffing, checksum validation, and address matching independently of host software.

Configuration is loaded at power-up from an external SPI EEPROM, enabling runtime customization of port count, removable status, power settings, overcurrent timers, LED polarity, and multi-language string descriptors - all without firmware changes.

Key Specifications

Pinout & Package

Package: 56-pin QFN (8 mm × 8 mm, 0.5 mm pitch), thermally enhanced with exposed pad. RoHS-compliant, lead-free, moisture sensitivity level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-port USB 2.0 hub controller applications.

Compared with CY7C65630-56LTXC, the CY7C65620 offers lower system cost and simpler power delivery for fixed 2-port use cases; versus UPD720114GA, it delivers superior integration density and reduced passive count at the expense of TT flexibility and self-power capability.

Availability

CY7C65620-56LTXC is available at Aetrix Electronics and suitable for monitor hubs, docking stations, and keyboard-integrated USB expansion requiring stable component supply across industrial temperature ranges and long-lifecycle production programs.

Supply support for CY7C65620-56LTXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) designs high-performance, low-power programmable system-on-chip solutions for USB, memory, and mixed-signal applications.

The EZ-USB HX2LP™ family targets ultra-low-power, space-constrained USB 2.0 hub implementations in consumer, industrial, and automotive peripherals - emphasizing BOM reduction through analog integration and EEPROM-driven configurability.

FAQ

Does CY7C65620-56LTXC support self-powered operation?

No. The CY7C65620-56LTXC is designed exclusively for bus-powered applications. It lacks the internal circuitry and pin assignments required for self-powered mode, unlike the CY7C65630 which supports both bus- and self-powered configurations. Power is derived solely from the upstream VBUS line via the VBUSPOWER pin, and internal regulation supplies core logic from that source.

What is the function of the PWR# and OVR# pins?

PWR#1 and PWR#2 are active-low, open-drain outputs that drive external N-channel MOSFETs to switch power to each downstream port. OVR#1 and OVR#2 are corresponding active-low, open-drain fault indicators asserting when overcurrent is detected on their respective ports. Both sets are EEPROM-configurable for polarity and latching behavior, enabling flexible power domain isolation strategies.

Can the CY7C65620-56LTXC operate without an external crystal?

No. A 24 MHz fundamental-mode crystal must be connected to the XIN/XOUT pins. The device integrates a PLL to derive all required USB clocks (48 MHz for high-speed, 12 MHz for full-speed), but it does not support external clock input or internal RC oscillation. Crystal load capacitance is specified at 12 pF, and stability over temperature is validated per industrial-grade requirements.

Is the CY7C65620-56LTXC pin-compatible with CY7C65640?

Yes - the CY7C65620-56LTXC is pin-for-pin compatible with CY7C65640 and CY7C65640A (TetraHub™) in the 56-pin QFN package. However, functionality differs: CY7C65640 supports four ports with dual TT, while CY7C65620 supports two ports with single TT. Firmware and EEPROM configuration must be updated accordingly; electrical pin behavior matches for shared signals like D+/D–, PWR#, OVR#, and SPI interface.