Infineon Technologies CY8C9560A-24AXI

Overview

CY8C9560A-24AXI from Cypress Semiconductor is a 60-bit I/O expander IC with integrated EEPROM and 16 independently configurable 8-bit PWM outputs, operating as dual I²C slave devices (I/O expander + serial EEPROM) at up to 400 kHz, supporting clock stretching, and featuring interrupt-driven input change detection and user-default restoration from nonvolatile memory. It is used in embedded control systems requiring scalable GPIO expansion with persistent configuration storage.

For engineers reviewing the CY8C9560A-24AXI datasheet, CY8C9560A-24AXI pinout, CY8C9560A-24AXI application, or CY8C9560A-24AXI equivalent, key selection criteria include I²C address flexibility via Extendable Soft Addressing (A0–A6), WD pin-controlled EEPROM write disable, programmable per-pin drive modes (strong drive, open-drain, pull-up/down, high-Z), and power-on restore of port/PWM defaults from EEPROM.

Technical Context

The device implements two independent I²C interfaces on a shared bus: one for register-mapped I/O control (using command-byte addressing), and another for EEPROM access (using 2-byte addressing). Its control unit decodes I²C transactions to route data to port registers, PWM configuration blocks, or EEPROM memory space.

All 60 I/O pins are individually assignable across four functional roles-input, output, quasi-bidirectional I/O, or PWM output-with per-pin drive mode selection (7 modes), inversion, direction, and interrupt masking. The 16 PWMs each support independent clock source selection (six options), period/pulse-width registers, and enable control.

Key Specifications

Pinout & Package

CY8C9560A-24AXI is housed in a 100-pin TQFP package (14 mm × 14 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions include 60 I/O bits, 7 address inputs (A0–A6), SCL/SDA, INT, WD, XRES, VDD, VSS, and internal oscillator connections.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I/O expander applications.

Compared with TCA6424A and PCA9555, CY8C9560A-24AXI provides 2.5× more I/O, integrated nonvolatile configuration storage, 16 hardware PWMs, and flexible I²C addressing-making it uniquely suited for complex embedded systems requiring self-contained, field-upgradable I/O behavior without host firmware overhead.

Availability

CY8C9560A-24AXI is available at Aetrix Electronics and suitable for industrial HMI panels, automotive body controllers, server rack management units, and medical diagnostic equipment requiring stable component supply and long-term design-in support.

Supply support for CY8C9560A-24AXI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) designs programmable system-on-chip solutions for embedded control, connectivity, and sensing applications, with emphasis on reliability and integration.

The CY8C95xxA family targets systems needing scalable, intelligent I/O expansion with built-in memory and timing resources-enabling host MCUs to offload GPIO management, retain configuration across power cycles, and simplify board-level interconnect.

FAQ

Does CY8C9560A-24AXI support standard-mode (100 kHz) and fast-mode (400 kHz) I²C?

Yes. The device fully complies with I²C specification v2.1 for both standard and fast modes. It requires the I²C master to support clock stretching during EEPROM writes and register updates, which is mandatory for reliable operation at either speed.

How is the 27 Kbyte EEPROM organized and accessed?

The EEPROM uses 2-byte addressing (AHI/ALO) spanning a 28 Kbyte address space, with 27 Kbyte allocated for user data. Access occurs through a dedicated I²C address (101000A0X); reads/writes use sequential byte addressing, and crossing 64-byte boundaries triggers automatic clock stretching during writes.

Can unused address pins (A1–A6) be repurposed as general-purpose I/O?

Yes. When not used for I²C addressing under the Extendable Soft Addressing scheme, pins A1–A6 function as GPIOs within GPort1 or GPort2, subject to their port-specific bit count limits (e.g., up to 4 bits on GPort2 depending on configuration).

What happens to I/O states during power-on reset?

Upon power-on reset (POR), the device loads factory-default configurations (pull-up bias, input mode) unless user defaults have been stored in EEPROM. If stored, those values-including port direction, drive mode, output state, and PWM setup-are automatically restored before the device becomes operational on the I²C bus.