Renesas D2-92643-LR

Overview

D2-92643-LR from Intersil is a dual SPST monolithic CMOS analog switch with TTL/CMOS-compatible digital inputs, 45 Ω max ON resistance, <150 ns turn-on time, and ±15 V analog signal range - used in precision sample-and-hold circuits and battery-operated data acquisition systems.

For engineers reviewing the D2-92643-LR datasheet, D2-92643-LR pinout, D2-92643-LR application, or D2-92643-LR equivalent, key selection criteria include guaranteed low charge injection (≤60 pC), rail-to-rail analog operation up to ±15 V, dual-channel matching (Δr_DS(ON) ≤ 5 Ω), and compatibility with single (+5 V to +34 V) or split (±5 V to ±17 V) supplies.

Technical Context

The D2-92643-LR implements two independent, bidirectional SPST switches using a high-voltage silicon-gate CMOS process that prevents latch-up and supports 44 V maximum V_+– differential. Its analog path exhibits low r_DS(ON) variation across ±15 V input range and minimal channel-to-channel crosstalk (−90 dB).

Control logic accepts standard TTL/CMOS thresholds (V_IL ≤ 0.8 V, V_IH ≥ 2.4 V) and drives both switches simultaneously via a single INx input per channel. The device operates with separate logic supply (VL) referenced to GND, enabling level-shifting between control and analog domains.

Key Specifications

Pinout & Package

16-lead TSSOP package (JEDEC MO-153-AB, pkg drawing M16.173), 4.4 mm × 5.0 mm body, 0.65 mm pitch, RoHS-compliant matte tin termination.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar analog switch applications.

Compared with MAX4617ESE+ and ADG1419BRUZ, D2-92643-LR uniquely balances rail-to-rail bipolar operation, moderate ON resistance, and cost-effective TSSOP packaging - making it optimal for industrial data acquisition and portable test gear where ±15 V signal integrity and <150 ns switching are essential but sub-10 pC injection is unnecessary.

Availability

D2-92643-LR is available at Aetrix Electronics and suitable for audio switching, battery-operated systems, and sample-and-hold circuits requiring stable component supply across extended temperature ranges (−40°C to +85°C) and long production lifecycles.

Supply support for D2-92643-LR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Intersil Corporation (now part of Renesas Electronics) designs high-performance analog and mixed-signal ICs for industrial, communications, and computing markets, certified to ISO9001 quality standards.

The DG401 family-including D2-92643-LR-was engineered for precision analog signal routing in environments demanding latch-up immunity, low charge injection, and wide supply flexibility, especially in data acquisition and test instrumentation.

FAQ

What is the maximum analog signal voltage range supported by the D2-92643-LR?

The D2-92643-LR supports an analog signal range of ±15 V when operated within its specified supply limits (e.g., V+ = +15 V, V− = −15 V). This allows full-rail operation with standard op-amp supplies and ensures linear switching across the entire input span without clipping or distortion. Exceeding ±15 V may activate internal clamping diodes and degrade performance.

Does the D2-92643-LR require separate logic and analog supplies?

Yes, the D2-92643-LR uses three distinct supply connections: V+ and V− for the analog signal path, and VL for the logic interface. VL must be referenced to GND and maintained between (GND − 0.3 V) and (V+ + 0.3 V). This separation enables level-shifting between 3.3 V/5 V control logic and ±15 V analog domains without external translators.

Can the D2-92643-LR operate from a single +12 V supply?

Yes, the D2-92643-LR supports single-supply operation from +5 V to +34 V. With V+ = +12 V, V− = GND, and VL = +5 V, it functions as a unipolar SPST switch handling 0 V to +12 V analog signals. However, the full ±15 V range requires split supplies (e.g., V+ = +15 V, V− = −15 V), and GND must remain connected as the logic reference.

What is the typical charge injection value for the D2-92643-LR, and why does it matter?

The D2-92643-LR has a typical charge injection of 60 pC, measured with CL = 10 nF and VG = 0 V. This parameter directly impacts sample-and-hold accuracy: injected charge causes a voltage step on the hold capacitor, leading to acquisition errors. At 60 pC, a 10 nF capacitor experiences a 6 mV step - acceptable for 12-bit systems but limiting for 16-bit precision without calibration.

Is the D2-92643-LR pin-compatible with other DG401 variants like DG401DY or DG401DVZ?

Yes, the D2-92643-LR shares identical pinout and electrical specifications with DG401DY (SOIC) and DG401DVZ (TSSOP), as confirmed by Intersil's FN3284 datasheet. All DG401-series devices use the same 16-pin topology, including NC placements and functional pin assignments. Layout reuse is fully supported across these variants, differing only in package type and RoHS compliance status.