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Renesas DA14580UNDB-P
- Part No.:
- DA14580UNDB-P
- Manufacturer:
- Renesas
- Category:
- RF, RFID, Wireless Evaluation Boards
- Package:
- Datasheet:
-
DA14580UNDB-P.pdf
- Description:
- PRO DAUGHTERBRD DA14580 WLCSP34
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
DA14580UNDB-P from Renesas Electronics is a Bluetooth Low Energy 4.2 System-on-Chip integrating ARM Cortex-M0 processor, dedicated BLE Link Layer hardware, 32 kB OTP, 42 kB SRAM, and fully integrated 2.4 GHz transceiver with -93 dBm sensitivity and 0 dBm output power. It operates as standalone application processor or data pump in hosted systems for wearables and sensor nodes.
For engineers reviewing the DA14580UNDB-P datasheet, DA14580UNDB-P pinout, DA14580UNDB-P application, or DA14580UNDB-P equivalent, key selection criteria include BLE 4.2 compliance, ultra-low-power Deep Sleep mode with retention RAM, OTA-updatable firmware, integrated DC-DC converter supporting coin/alkaline batteries, and QFN40 package with 24 GPIOs.
Technical Context
The DA14580UNDB-P implements BLE protocol stack in ROM (84 kB), executes application code from OTP-mirrored SRAM, and offloads Link Layer processing to dedicated hardware-reducing CPU load and enabling deterministic timing for advertising, connection, and scanning. Its dual-oscillator clock system uses 16 MHz crystal (±20 ppm) for active mode and 32.768 kHz crystal (±50 ppm) or RCX for low-power sleep.
Power management includes integrated buck/boost DC-DC converter with four supply pins, retention SRAM partitioning (2 kB + 2 kB + 3 kB + 1 kB), and hardware AES-128 encryption engine. Radio interface requires no external matching network via single-wire RFIOp/RFIOm connection to antenna.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| BLE Standard | Bluetooth 4.2 compliant; meets ETSI EN 300 328, FCC Part 15, ARIB STD-T66 for global regulatory approval. |
| CPU Core | ARM Cortex-M0 @ 16 MHz; delivers 0.9 dMIPS/MHz for application logic while BLE Link Layer runs in parallel on dedicated hardware. |
| Memory | 32 kB OTP (application/profile storage), 42 kB SRAM (code/data runtime), 84 kB ROM (BLE stack), 8 kB retention SRAM (deep-sleep state preservation). |
| Radio Performance | -93 dBm receiver sensitivity; 0 dBm TX output power; Near Field Mode at -20 dBm; single-wire RFIO interface eliminates external RF matching components. |
| Power Supply | Supports 3.0 V coin cell (VBAT3V) or 1.5 V alkaline/NiMH (VBAT1V); integrated buck/boost DC-DC enables operation across battery chemistries without external regulators. |
| Peripherals | 2× UART (1 MBd, HW flow control), SPI+, I²C (100/400 kHz), 4-channel 10-bit ADC, quadrature decoder (3-axis), 24 GPIOs (QFN40 package). |
Pinout & Package
DA14580UNDB-P is packaged in QFN40 (5 mm × 5 mm, 0.5 mm pitch) with exposed thermal pad. Pin count and I/O allocation match the QFN40 variant specified in ordering information and pin description tables.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0_0–P0_7 | General-purpose I/O | 8-bit port with configurable pull-up/down; retains state during Deep Sleep; supports ADC[0–3] mapping on P0_0–P0_3. |
| P1_0–P1_3, P1_4/SW_CLK, P1_5/SW_DIO | GPIO / Debug interface | 4 GPIOs + SWD debug pins; SW_CLK and SW_DIO default to JTAG clock/data but function as GPIOs when debug disabled. |
| P2_0–P2_9 | General-purpose I/O | 10-bit port with retention; available only on QFN40/QFN48 packages; supports UART2, SPI, I²C, and quadrature decoder functions. |
| XTAL16Mp/m, XTAL32Kp/m | Clock inputs/outputs | 16 MHz crystal (±20 ppm) and 32.768 kHz crystal (±50 ppm) interfaces; essential for BLE timing accuracy and low-power sleep clocking. |
| RFIOp / RFIOm | RF transceiver interface | Differential 50 Ω RF port; enables direct antenna connection without external balun, matching network, or RX/TX switch. |
| VBAT3V / VBAT1V / VDCDC / SWITCH | Power management | Supports dual-battery input; VDCDC output powers core; SWITCH connects external inductor for integrated buck/boost DC-DC operation. |
Key Features
| Feature | Design Value |
|---|---|
| BLE 4.2 Protocol Stack | ROM-resident L2CAP, SM, ATT, GATT, GAP - certified and field-proven; enables rapid development of SIG-compliant profiles. |
| Dedicated Link Layer Processor | Hardware-accelerated BLE baseband processing ensures deterministic timing for advertising, scanning, and connection events without CPU intervention. |
| OTA Firmware Updates | Secure over-the-air updates enabled by OTP architecture and boot ROM sequence; supports customer application and profile upgrades post-deployment. |
| Ultra-Low-Power Deep Sleep | Retention RAM partitions preserve BLE context and application variables; wake-up from Deep Sleep in <100 µs using wake-up timer or GPIO event. |
| Integrated Power Management | Buck/boost DC-DC converter with single-inductor topology reduces BOM count; supports 1.5 V–3.3 V input range and maintains stable core voltage across battery discharge. |
Applications
| Wireless Wearable Sensor Hub | Smart Home Beacon Node |
|---|---|
|
Use Scenario: Compact wearable device measuring heart rate, motion, and temperature with BLE telemetry to smartphone. IC Role / Device Role / Timing Role: Standalone application processor executing sensor fusion algorithms and BLE GATT server; manages periodic advertising and connection intervals per BLE 4.2 spec. Use Value: 42 kB SRAM enables local buffering of sensor data; 32 kB OTP stores calibrated firmware; -93 dBm sensitivity ensures reliable link at 10+ meter range in body-worn configurations. |
Use Scenario: Battery-powered indoor beacon broadcasting location-aware services to mobile devices in retail or office environments. IC Role / Device Role / Timing Role: Data pump transmitting preconfigured iBeacon/Eddystone frames; leverages Deep Sleep between advertising events to extend coin-cell life beyond 1 year. Use Value: Integrated DC-DC allows direct 3.0 V coin cell operation; 0 dBm TX power meets EIRP limits while maintaining coverage; QFN40 footprint enables compact PCB layout. |
| Industrial Asset Tag | Medical Diagnostic Patch |
|
Use Scenario: Ruggedized tag monitoring equipment temperature, humidity, and tamper status in factory settings with periodic BLE reporting. IC Role / Device Role / Timing Role: Hosted system node interfacing with external sensors via I²C/ADC; schedules BLE connections based on event triggers or fixed intervals. Use Value: 24 GPIOs support multiple digital and analog sensors; hardware AES-128 secures sensor data before transmission; retention RAM preserves last-read values during sleep. |
Use Scenario: Disposable skin patch collecting ECG and skin impedance data for remote patient monitoring via BLE to gateway. IC Role / Device Role / Timing Role: Ultra-low-power SoC managing analog front-end sampling, signal preprocessing, and encrypted BLE packetization under strict medical battery-life requirements. Use Value: 10-bit ADC with 4 channels digitizes biopotential signals; 8 kB retention SRAM holds critical diagnostic buffers; BLE 4.2 privacy features protect patient identity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Bluetooth Low Energy SoC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| nRF52832-QFAA | ARM Cortex-M4F @ 64 MHz; 64 kB RAM; no integrated DC-DC; requires external regulator for coin-cell use. | Higher compute throughput for complex sensor fusion; less suitable for cost-sensitive, ultra-low-power coin-cell designs without external PMIC. | Select nRF52832-QFAA when application demands floating-point math or larger RAM footprint; verify external power design for battery longevity. |
| CC2640R2F | ARM Cortex-M3 @ 48 MHz; 275 kB ROM (BLE stack + drivers); 20 kB RAM; integrated DC-DC; TI's SimpleLink SDK ecosystem. | Stronger software toolchain and long-term SDK support; slightly higher active current than DA14580UNDB-P in BLE advertising mode. | Choose CC2640R2F for projects requiring mature TI SDK integration and extended lifecycle assurance; confirm RF layout compatibility with QFN40 footprint. |
Compared with nRF52832-QFAA and CC2640R2F, DA14580UNDB-P offers lower system BOM cost via integrated buck/boost DC-DC and smaller QFN40 footprint, while delivering BLE 4.2 compliance and sub-4 mA active current - ideal for space-constrained, single-battery consumer devices.
Availability
DA14580UNDB-P is available at Aetrix Electronics and suitable for wireless wearables, smart beacons, industrial asset tags, and disposable medical patches requiring stable component supply and long-term production continuity.
Supply support for DA14580UNDB-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics acquired Dialog Semiconductor in 2022, integrating its ultra-low-power connectivity portfolio into a broader embedded solutions ecosystem.
The DA14580UNDB-P belongs to Dialog's legacy BLE SoC product line, designed specifically for battery-operated IoT endpoints where minimal size, multi-year coin-cell life, and certified BLE 4.2 interoperability are mandatory.
FAQ
What is the package type and pin count of DA14580UNDB-P?
DA14580UNDB-P uses a QFN40 package (5 mm × 5 mm, 0.5 mm pitch) with 40 terminals, including 24 general-purpose I/Os, dedicated RFIO pins, dual crystal interfaces, and power management terminals. This matches the DA14580-01AT1/AT2 ordering variants and is confirmed in the official datasheet Section 2 (Pinout) and Table 2 (Ordering Information).
Does DA14580UNDB-P support over-the-air (OTA) firmware updates?
Yes, DA14580UNDB-P supports secure OTA firmware updates via its flexible memory architecture: application code resides in OTP, while the boot ROM and qualified BLE stack are stored in ROM. The system enables field-upgradable customer profiles and firmware patches using the documented OTA mechanism described in Application Note AN-B-002.
What power sources does DA14580UNDB-P support?
DA14580UNDB-P supports both 3.0 V coin cells (connected to VBAT3V) and 1.5 V alkaline/NiMH batteries (connected to VBAT1V), thanks to its integrated buck/boost DC-DC converter. The DC-DC output (VDCDC) powers the core logic, and the SWITCH pin connects to an external inductor - enabling efficient operation across battery chemistries without external regulators.
Is DA14580UNDB-P Bluetooth 4.2 certified?
Yes, DA14580UNDB-P is fully compliant with Bluetooth Core Specification v4.2 and carries certifications for ETSI EN 300 328 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan). Its qualified BLE protocol stack is stored in ROM, and the radio meets all RF conformance requirements defined in the Bluetooth SIG test specifications.
What is the role of the retention SRAM in DA14580UNDB-P?
DA14580UNDB-P includes 8 kB of retention SRAM divided into four blocks (2 kB + 2 kB + 3 kB + 1 kB) that remain powered during Deep Sleep mode. These blocks preserve BLE connection context, application variables, and processor stack - enabling wake-up in under 100 µs and eliminating full reinitialization overhead, which is critical for battery life in intermittent-sensing applications.
DA14580UNDB-P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- SmartBond™
- Packaging:
- Box
- Product Status:
- Obsolete
- Type:
- Transceiver; Bluetooth® Smart 4.x Low Energy (BLE)
- Frequency:
- 2.4GHz
- Contents:
- Board(s)
- Utilized IC / Part:
- DA14580
DA14580UNDB-P FAQ
1.How can I place an order for DA14580UNDB-P through Aetrix?
Please submit a Request for Quotation (RFQ) for DA14580UNDB-P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DA14580UNDB-P reliable?
The price and inventory of DA14580UNDB-P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DA14580UNDB-P is usually 5 days.
3.What payment methods are accepted for DA14580UNDB-P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DA14580UNDB-P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DA14580UNDB-P?
DA14580UNDB-P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DA14580UNDB-P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DA14580UNDB-P?
For technical support, including DA14580UNDB-P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DA14580UNDB-P requirements.
6.How does Aetrix verify that DA14580UNDB-P is sourced from the original manufacturer or authorized distributors?
All DA14580UNDB-P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DA14580UNDB-P meets industry standards.
7.What is the process for return or replacement of DA14580UNDB-P?
All DA14580UNDB-P units undergo pre-shipment inspection (PSI). If there is an issue with DA14580UNDB-P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DA14580UNDB-P part is unused and in its original packaging.
Return procedure for DA14580UNDB-P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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