Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - DC DC Switching Regulators

Renesas DA9122-E0V72

Name: DA9122-E0V72
Brand: Renesas
SKU: DA9122-E0V72
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: DA9122-E0V72

Manufacturer:: Renesas

Category:: Voltage Regulators - DC DC Switching Regulators

Package:: 24-UFBGA, WLCSP

Datasheet:: DA9122-E0V72.pdf

Description:: IC REG BCK ADJ 5A/5A DL 24WLCSP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,622

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

DA9122-E0V72 from Renesas Electronics is a dual-channel synchronous buck DC-DC converter PMU designed for CPU/GPU and DDR memory rail regulation in space-constrained mobile applications. It delivers up to 5 A per channel across 0.3 V–1.9 V output, operates from 2.5 V–5.5 V input, features 4 MHz switching frequency, ±1 % static output accuracy, and integrated remote-sense differential feedback for point-of-load regulation.

For engineers reviewing the DA9122-E0V72 datasheet, DA9122-E0V72 pinout, DA9122-E0V72 application, or DA9122-E0V72 equivalent, key selection considerations include its 24WLCSP package (2.48 mm × 1.68 mm), I²C-compatible FM+ interface with programmable GPIOs, dynamic voltage control (DVC) with configurable slew rates, and integrated thermal/overcurrent protection without external sensing components.

Technical Context

The DA9122-E0V72 integrates two independent single-phase synchronous buck converters with fully integrated high-side and low-side MOSFETs (RON_PMOS = 36 mΩ, RON_NMOS = 17 mΩ at VIN = 3.7 V). Each channel supports programmable soft-start, ramped DVC transitions (10 mV per 0.5–8 µs), and automatic PWM/PFM mode selection based on load current.

It implements differential remote sensing via FB1P/FB1N and FB2P/FB2N pins for ±1 % static accuracy, includes dedicated thermal warning (115–135 °C) and critical shutdown (130–150 °C) thresholds, and provides interrupt reporting (nIRQ) for faults including overtemperature, overcurrent, and power-good loss - all managed through an I²C register map with 24-bit address support.

Key Specifications

Parameter	Value and Actual Design Meaning
Input voltage	2.5 V to 5.5 V - compatible with single-cell Li-ion batteries and standard 3.3 V/5 V system rails.
Output voltage range	0.3 V to 1.9 V per channel - covers core logic, GPU, and DDR memory supply requirements.
Max output current	5 A per channel - sufficient for high-performance mobile SoC core and graphics rails.
Switching frequency	4 MHz nominal - enables use of ultra-small 0.10 µH inductors and reduces output capacitor size.
Output accuracy	±1 % static (≥1 V), ±10 mV static (<1 V) - ensures tight regulation under line/load transients for sensitive digital loads.
Interface	I²C-compatible FM+ (up to 1 MHz) - supports fast configuration and real-time DVC updates in multi-rail systems.
Operating temperature	−40 °C to +85 °C ambient - qualified for smartphone, tablet, and infotainment environments.

Pinout & Package

DA9122-E0V72 is housed in a 24-ball WLCSP package (2.48 mm × 1.68 mm, 0.4 mm pitch) optimized for ultra-thin mobile PCBs. The package supports solder reflow per JEDEC J-STD-020 and has MSL3 rating.

Pin/Terminal	Circuit Role	Design Meaning
PVDD1, PVDD2	Power input for Buck1/Buck2 power stages	Must be decoupled with 10 µF capacitors; shared with AVDD to minimize noise coupling into analog control circuitry.
LX1, LX2	Switch node outputs	Connect directly to 0.10 µH inductors; high di/dt paths require short, low-inductance routing to minimize EMI and voltage spikes.
FB1P/FB1N, FB2P/FB2N	Differential feedback inputs	Enable remote sensing: FBxP connects to VOUTx at load, FBxN connects to local ground at load - cancels PCB IR drop for ±1 % accuracy.
SCL/GPIO3, SDA/GPIO4	I²C clock/data or configurable GPIO	Support FM+ I²C (1 MHz) by default; can be repurposed as push-pull outputs (15 mA drive) for system signaling.
IC_EN	Chip enable input	Active-high control: asserts internal POR and powers up analog/digital blocks; <1 µA shutdown current when low.
CONF/GPIO0	Configuration select or GPIO	Determines I²C address (0x60–0x67) when used as input; configurable as bidirectional I/O with 2–120 kΩ pull-up/down resistors.

Key Features

Feature	Design Value
Dual independent buck regulators	Each delivers 5 A with separate voltage registers (A/B), enabling dynamic core/GPU voltage scaling and retention modes without host software intervention.
Programmable DVC slew rate	Configurable per channel (10 mV per 0.5/1/2/4/8 µs) - balances transient response speed against output overshoot and system stability.
Integrated thermal protection	Two-tier monitoring: warning flag at 115–135 °C triggers host alert; critical shutdown at 130–150 °C disables both bucks immediately to prevent damage.
Remote-sense differential feedback	Eliminates PCB trace resistance error - maintains ±1 % output accuracy even with >100 mΩ path impedance between IC and load.
Auto PWM/PFM mode switching	Optimizes light-load efficiency (88 µA quiescent in PFM) while preserving fast transient response in forced PWM during active processing.

Applications

Smartphone Core Power	Tablet GPU Rail
Use Scenario: Regulating application processor cores (e.g., ARM Cortex-A series) during burst workloads and deep sleep states. IC Role / Device Role / Timing Role: Dual-channel buck regulator providing independent, dynamically scaled VDD_CPU and VDD_GPU supplies with sub-20 µs turn-on time and DVC coordination. Use Value: Enables adaptive voltage/frequency scaling (AVS) to reduce average power by >30 % versus fixed-voltage operation while maintaining timing margin.	Use Scenario: Supplying graphics processing units in Android/iOS tablets requiring rapid voltage transitions between rendering and idle states. IC Role / Device Role / Timing Role: High-bandwidth buck converter delivering 5 A at 0.8–1.2 V with 10 mV/µs DVC slew - synchronized to GPU clock domain via I²C writes. Use Value: Reduces GPU rail overshoot to <±5 % during 0→5 A load steps, preventing timing violations in high-speed pixel pipelines.
SIPP Module DDR Supply	Wi-Fi Module SoC Core
Use Scenario: Powering LPDDR4/LPDDR5 memory interfaces in compact SIPP modules where board area is constrained and thermal dissipation is limited. IC Role / Device Role / Timing Role: Precision 0.3–1.1 V buck regulator with differential remote sensing - compensating for voltage drop across fine-pitch BGA interconnects. Use Value: Maintains DDR VDDQ regulation within ±10 mV across temperature and load, ensuring signal integrity at 4266 MT/s data rates.	Use Scenario: Supplying Wi-Fi 6/6E baseband SoCs (e.g., QCA6391, BCM4375) in thin client and IoT edge devices. IC Role / Device Role / Timing Role: Low-noise, fast-transient dual buck managing RF and digital core domains - with independent PG status reporting via GPIOs. Use Value: Guarantees clean 0.85 V core supply during 802.11ax packet bursts, eliminating RF desense caused by supply droop >30 mV.

Smartphone Core Power

Tablet GPU Rail

Use Scenario: Regulating application processor cores (e.g., ARM Cortex-A series) during burst workloads and deep sleep states.

IC Role / Device Role / Timing Role: Dual-channel buck regulator providing independent, dynamically scaled VDD_CPU and VDD_GPU supplies with sub-20 µs turn-on time and DVC coordination.

Use Value: Enables adaptive voltage/frequency scaling (AVS) to reduce average power by >30 % versus fixed-voltage operation while maintaining timing margin.

Use Scenario: Supplying graphics processing units in Android/iOS tablets requiring rapid voltage transitions between rendering and idle states.

IC Role / Device Role / Timing Role: High-bandwidth buck converter delivering 5 A at 0.8–1.2 V with 10 mV/µs DVC slew - synchronized to GPU clock domain via I²C writes.

Use Value: Reduces GPU rail overshoot to <±5 % during 0→5 A load steps, preventing timing violations in high-speed pixel pipelines.

SIPP Module DDR Supply

Wi-Fi Module SoC Core

Use Scenario: Powering LPDDR4/LPDDR5 memory interfaces in compact SIPP modules where board area is constrained and thermal dissipation is limited.

IC Role / Device Role / Timing Role: Precision 0.3–1.1 V buck regulator with differential remote sensing - compensating for voltage drop across fine-pitch BGA interconnects.

Use Value: Maintains DDR VDDQ regulation within ±10 mV across temperature and load, ensuring signal integrity at 4266 MT/s data rates.

Use Scenario: Supplying Wi-Fi 6/6E baseband SoCs (e.g., QCA6391, BCM4375) in thin client and IoT edge devices.

IC Role / Device Role / Timing Role: Low-noise, fast-transient dual buck managing RF and digital core domains - with independent PG status reporting via GPIOs.

Use Value: Guarantees clean 0.85 V core supply during 802.11ax packet bursts, eliminating RF desense caused by supply droop >30 mV.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel buck regulator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS65988DHFR	Single-chip USB-C PD controller + dual buck (3 A each); 2.7–5.5 V input; no remote sensing; ±2 % accuracy.	Targeted at USB-C dock/monitor power delivery, not mobile SoC core rails.	Choose when USB-C PD negotiation and Type-C port control are required alongside regulation.
RTQ2134BGQW	Dual 4 A buck with 2.5–5.5 V input; 0.6–1.8 V output; ±1.5 % accuracy; no DVC or remote sense; 16-pin QFN.	Designed for industrial embedded systems with less stringent size/thermal constraints.	Choose when WLCSP footprint is not required and I²C configurability is secondary to cost and simplicity.

Compared with TPS65988DHFR and RTQ2134BGQW, DA9122-E0V72 uniquely combines 5 A per channel, 24WLCSP packaging, differential remote sensing, and programmable DVC - making it optimal for next-generation mobile SoC power delivery where accuracy, size, and dynamic response are co-constrained.

Availability

DA9122-E0V72 is available at Aetrix Electronics and suitable for smartphone core power, tablet GPU rail, and SIPP module DDR supply applications requiring stable component supply across high-volume production cycles.

Supply support for DA9122-E0V72 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog power, and connectivity solutions for automotive, industrial, and consumer markets.

The DA9122-E0V72 belongs to Renesas' DA-series power management units, engineered specifically for high-efficiency, ultra-compact power delivery in battery-powered mobile SoCs and memory modules.

FAQ

What is the maximum supported I²C clock frequency for DA9122-E0V72?

The DA9122-E0V72 supports Fast Mode Plus (FM+) I²C operation up to 1 MHz. This allows rapid register access for dynamic voltage control updates and real-time fault monitoring. The device meets I²C timing specifications including tRISE ≤ 1000 ns and tFALL ≤ 300 ns under 150 pF bus capacitance, ensuring robust communication in dense mobile PCB layouts. DA9122-E0V72's FM+ interface enables sub-microsecond DVC command execution critical for CPU/GPU load tracking.

Does DA9122-E0V72 support remote sensing, and how is it implemented?

Yes, DA9122-E0V72 implements true differential remote sensing via dedicated FB1P/FB1N and FB2P/FB2N pin pairs. FBxP connects to the output voltage at the load point, while FBxN connects to the local ground reference at that same point - rejecting voltage drop across PCB traces. This architecture achieves ±1 % static output accuracy regardless of trace resistance, a capability confirmed in the datasheet's "Buck Electrical Characteristics" table. DA9122-E0V72's remote sensing is integral to its use in SIPP modules and smartphones where power delivery path impedance varies significantly.

What thermal protection mechanisms does DA9122-E0V72 provide?

DA9122-E0V72 incorporates dual-level thermal protection: a thermal warning flag activates at 115–135 °C (configurable via register), triggering an interrupt (E_TEMP_WARN) to alert the host processor; a thermal critical threshold at 130–150 °C forces immediate shutdown of both buck converters. Both flags are latched and readable via I²C status registers (TEMP_WARN, TEMP_CRIT). The device's 32.7 °C/W θJA enables sustained 5 A operation in thermally optimized layouts. DA9122-E0V72's protection requires no external components - all sensing and response logic is integrated.

Can DA9122-E0V72 operate with different output voltages on each channel?

Yes, DA9122-E0V72 supports independent voltage programming per channel: Buck1 and Buck2 each have two programmable voltage registers (A and B), allowing distinct output levels (e.g., 0.85 V for CPU core and 1.1 V for GPU). Voltage selection is controlled either by I²C register writes (CH1_VSEL/CH2_VSEL) or via CONF/GPIO0 pin state. The device also supports retention-mode voltages, enabling low-power states without host intervention. DA9122-E0V72's dual-voltage flexibility is explicitly documented in Section 4.1.3 ("Output Voltage Selection") of its datasheet.

What is the minimum inductor value supported by DA9122-E0V72?

DA9122-E0V72 is characterized and specified for use with 0.10 µH inductors per channel, with tolerance of −50 % to +20 % (i.e., 0.05 µH to 0.12 µH). This ultra-low inductance enables compact designs and high-frequency operation at 4 MHz. The datasheet specifies DCR limits (30–50 mΩ) and capacitor requirements (2 × 10 µF per phase) to ensure stability and transient performance. DA9122-E0V72's 0.10 µH requirement is validated across input (2.5–5.5 V) and output (0.3–1.9 V) ranges, and is a key enabler of its 24WLCSP form factor.

DA9122-E0V72 Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: -

Package/Case:: 24-UFBGA, WLCSP

Packaging:: Tape & Reel (TR)

Product Status:: Active

Function:: Step-Down

Output Configuration:: Positive

Topology:: Buck

Output Type:: Adjustable

Number of Outputs:: 2

Voltage - Input (Min):: 2.5V

Voltage - Input (Max):: 5.5V

Voltage - Output (Min/Fixed):: 0.3V

Voltage - Output (Max):: 1.9V

Current - Output:: 5A, 5A

Frequency - Switching:: 4MHz

Synchronous Rectifier:: Yes

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 24-WLCSP (2.48x1.68)

DA9122-E0V72 FAQ

1.How can I place an order for DA9122-E0V72 through Aetrix?

Please submit a Request for Quotation (RFQ) for DA9122-E0V72 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for DA9122-E0V72 reliable?

The price and inventory of DA9122-E0V72 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DA9122-E0V72 is usually 5 days.

3.What payment methods are accepted for DA9122-E0V72?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DA9122-E0V72 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for DA9122-E0V72?

DA9122-E0V72 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your DA9122-E0V72 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for DA9122-E0V72?

For technical support, including DA9122-E0V72 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DA9122-E0V72 requirements.

6.How does Aetrix verify that DA9122-E0V72 is sourced from the original manufacturer or authorized distributors?

All DA9122-E0V72 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DA9122-E0V72 meets industry standards.

7.What is the process for return or replacement of DA9122-E0V72?

All DA9122-E0V72 units undergo pre-shipment inspection (PSI). If there is an issue with DA9122-E0V72, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The DA9122-E0V72 part is unused and in its original packaging.

Return procedure for DA9122-E0V72:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…