Renesas DA9131-XXRT1
- Part No.:
- DA9131-XXRT1
- Manufacturer:
- Renesas
- Package:
- 24-PowerUFQFN
- Datasheet:
-
DA9131-XXRT1.pdf
- Description:
- IC REG BUCK ADJ 10A 24FCQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,169
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Product details
Overview
DA9131-XXRT1 from Renesas Electronics is a dual-channel, single-phase synchronous buck PMIC designed to supply CPU/GPU core and DDR memory rails in mobile, portable, and SIPP-module applications. It delivers up to 5 A per channel across 0.3 V–1.9 V output range from a 2.8 V–5.5 V input, operates at 4 MHz switching frequency, and integrates pass FETs with remote sensing for ±1 % static output accuracy.
For engineers reviewing the DA9131-XXRT1 datasheet, DA9131-XXRT1 pinout, DA9131-XXRT1 application, or DA9131-XXRT1 equivalent, key selection criteria include dual-rail dynamic voltage control (DVC) via I²C or GPIO, wettable-flank 24-pin FCQFN (3.3 mm × 4.8 mm) package compatibility, thermal protection with junction monitoring, and support for 220 nH inductors with minimal external components.
Technical Context
The DA9131-XXRT1 implements two independent, current-mode controlled buck converters with integrated high-side and low-side MOSFETs-eliminating need for external FETs or Schottky diodes. Each channel supports programmable soft-start, over-current protection with configurable ILIM register, and remote differential feedback (FB1P/FB1N, FB2P/FB2N) for precise load-point regulation under PCB routing variations.
Its FM+-compatible I²C interface (up to 1 MHz) enables real-time DVC, rail sequencing, fault reporting (via nIRQ), and multi-device addressing through CONF/GPIO0 configuration. Internal supervision includes junction temperature monitoring, power-good (PG) assertion with ±80 mV hysteresis, and automatic thermal shutdown at TCRIT (150 °C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.8 V to 5.5 V - supports single-cell Li-ion, USB PD, and wide-input industrial supplies without pre-regulation. |
| Output Voltage Range | 0.3 V to 1.9 V in 10 mV steps - matches modern SoC core/DDR voltage requirements with fine-grained DVC control. |
| Max Output Current | 5 A per channel - sufficient for high-performance CPU/GPU cores and DDR4/DDR5 memory rails. |
| Switching Frequency | 4 MHz nominal - enables use of ultra-small 220 nH inductors and reduces output capacitance footprint. |
| Output Accuracy | ±1 % (static, VOUT ≥ 1 V) - ensures stable operation of voltage-sensitive digital logic without margining overhead. |
| Package | 24-pin FCQFN, 3.3 mm × 4.8 mm, wettable flanks - supports automated optical inspection (AOI) and reliable reflow soldering in high-density layouts. |
| Ambient Temp Range | −40 °C to +105 °C - qualified for extended industrial and automotive-grade (DA9131-A) environments. |
Pinout & Package
DA9131-XXRT1 is housed in a 24-pin FCQFN package (3.3 mm × 4.8 mm, 0.4 mm pitch) with wettable flanks for solder joint inspection. Thermal pad exposed on underside connects to PGND plane for optimal heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PVDD1, PVDD2 (pins 1–2, 15–16) | Power Supply Input | Dedicated input rails for Channel 1 and Channel 2-decoupling required per channel to minimize cross-talk. |
| LX1, LX2 (pins 23–24, 17–18) | Switch Node Output | High-current switched outputs driving external 220 nH inductors; require short, low-inductance PCB traces. |
| FB1P/FB1N, FB2P/FB2N (pins 4–5, 12–13) | Differential Feedback Inputs | Enable Kelvin-sense remote voltage regulation-critical for maintaining ±1 % accuracy across board voltage drops. |
| SCL/GPIO3, SDA/GPIO4 (pins 3, 6) | I²C Interface / GPIO | FM+-compatible bidirectional bus pins; default as I²C, configurable as general-purpose I/O after initialization. |
| IC_EN (pin 7) | Global Enable Input | Active-high enable controlling both channels; ties to system power-on reset or host processor GPIO. |
| CONF/GPIO0 (pin 10) | Configuration Select | Resistor-programmable I²C slave address selection-supports up to four DA9131-XXRT1 devices on one bus. |
| nIRQ (pin 11) | Interrupt Output | Open-drain fault indicator asserting on over-temperature, over-current, or power-good failure-connects directly to SoC interrupt controller. |
| PGND (pins 19–22) | Power Ground | High-current return path for both buck channels; must be connected to thermal pad and low-impedance ground plane. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent buck regulators | Enables simultaneous, isolated power delivery to CPU core and DDR memory with independent voltage and sequencing control. |
| Integrated MOSFETs + remote sensing | Eliminates external FETs, diodes, and sense resistors-reduces BOM count by ≥6 components per channel and improves load regulation accuracy. |
| Dynamic Voltage Control (DVC) | Allows real-time voltage scaling via I²C write or dedicated GPIO-reducing dynamic power consumption during low-load states. |
| Programmable soft-start | Configurable ramp rate prevents input inrush current spikes-protects upstream power sources and avoids brown-out during power-up. |
| Thermal & over-current protection | On-die temperature sensor and cycle-by-cycle current limiting operate autonomously-no external IC or firmware required for safe operation. |
Applications
| Mobile Application Processor Power | DDR Memory Rail Supply |
|---|---|
|
Use Scenario: Powering ARM-based application processors (e.g., i.MX8, Snapdragon) requiring tightly regulated core (VDD_CPU) and GPU (VDD_GPU) rails. IC Role / Device Role / Timing Role: Dual-channel PMIC delivering synchronized, independently controlled 0.6–1.2 V rails with DVC-triggered voltage scaling during DVFS transitions. Use Value: Enables sub-100 ns response to load transients and maintains ±1 % output accuracy across −40 °C to +105 °C ambient-critical for SoC stability and performance binning. |
Use Scenario: Supplying DDR4/DDR5 memory subsystems in portable computing and edge AI devices. IC Role / Device Role / Timing Role: Provides 1.1 V or 1.8 V DDR termination and VDDQ rails with remote sensing to compensate for PCB IR drop between PMIC and memory IC. Use Value: Achieves <50 mV load transient deviation (±5 %) and supports fast rail ramp-up for memory initialization sequences-reducing boot time by up to 12 ms. |
| SIPP Module Integration | Industrial Edge Controller Power |
|
Use Scenario: Embedded power solution inside single-in-line pin (SIPP) modules housing SoC + DRAM combinations for space-constrained IoT gateways. IC Role / Device Role / Timing Role: Compact 24-pin FCQFN PMIC co-located with memory and processor die-minimizes interconnect inductance and improves EMI performance. Use Value: Delivers 218 mm² total solution area with 220 nH inductors-enabling module height <1.2 mm while meeting AEC-Q100 Grade 2 thermal specs. |
Use Scenario: Power management in DIN-rail mounted PLCs and smart metering systems operating in harsh industrial environments. IC Role / Device Role / Timing Role: Dual-rail regulator supplying FPGA I/O banks and real-time MCU cores with independent fault reporting via nIRQ pin. Use Value: Integrated over-temperature protection triggers graceful shutdown at 150 °C junction-prevents field failures without external thermal ICs or firmware polling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-buck PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65917B1RSLR | Single 2.5 V–4.8 V input, 3 buck + 5 LDO architecture; no remote sensing; 2.2 MHz max switching frequency. | Targeted at TI Sitara AMx platforms; lacks DVC via GPIO and wettable-flank package. | Preferred when LDO integration and TI ecosystem tooling outweigh need for 4 MHz operation and Kelvin sensing. |
| MPQ4572GQBE-AEC1 | Automotive-qualified dual 3 A buck; 2.5 V–6.5 V input; no I²C interface; fixed 500 kHz–2.2 MHz spread-spectrum operation. | Designed for ASIL-B ADAS camera modules; no DVC or programmable soft-start. | Chosen where functional safety certification and spread-spectrum EMI reduction are mandatory, but digital control is unnecessary. |
Compared with TPS65917B1RSLR and MPQ4572GQBE-AEC1, DA9131-XXRT1 uniquely combines 4 MHz operation, differential remote sensing, GPIO-driven DVC, and wettable-flank FCQFN-making it optimal for compact, thermally constrained, digitally adaptive power systems requiring precision regulation.
Availability
DA9131-XXRT1 is available at Aetrix Electronics and suitable for mobile SoC power, DDR memory supply, and SIPP module integration requiring stable component supply, long-term lifecycle assurance, and automotive-grade variants.
Supply support for DA9131-XXRT1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog power, and connectivity solutions for automotive, industrial, and enterprise markets.
The DA9131-XXRT1 belongs to Renesas' Power Management IC product line, engineered specifically for high-efficiency, digitally controllable power delivery in battery-powered and thermally constrained portable systems.
FAQ
What is the maximum supported inductor value for DA9131-XXRT1?
The DA9131-XXRT1 is optimized for 220 nH inductors (−50 %/+20 % tolerance), as specified in Table 8 of the datasheet. Using larger inductors increases peak-to-peak ripple current and reduces transient response speed-potentially violating the ±5 % dynamic load regulation spec. The 4 MHz switching frequency and integrated FETs are tuned for this value; deviations require revalidation of efficiency, thermal performance, and stability.
Does DA9131-XXRT1 support power sequencing between its two output rails?
Yes, DA9131-XXRT1 supports programmable power sequencing via its I²C interface and register-controlled EN1/EN2 enable bits. The SYS_CONFIG_0 register (0x0B) allows setting delay intervals between VOUT1 and VOUT2 startup/shutdown, enabling strict ordering for SoC+DDR or core+peripheral rail dependencies without external timing circuitry.
Can DA9131-XXRT1 operate without an I²C host controller?
Yes, DA9131-XXRT1 supports standalone operation using GPIO-based DVC and fixed-voltage configuration. The CONF/GPIO0 pin selects I²C address, while GPIO1–GPIO4 can be configured as DVC inputs to adjust VOUT1/VOUT2 in discrete steps-enabling full functionality in systems lacking I²C infrastructure.
What is the purpose of the wettable flanks on the DA9131-XXRT1 FCQFN package?
The wettable flanks on the DA9131-XXRT1 package expose solderable sidewalls on all perimeter pins, enabling automated optical inspection (AOI) of solder joint quality during reflow. This feature is critical for high-reliability manufacturing-especially in automotive and industrial applications-where void-free solder joints directly impact thermal resistance and long-term power delivery stability.
How does DA9131-XXRT1 handle over-temperature conditions?
DA9131-XXRT1 incorporates an on-die temperature sensor that triggers thermal warning (T_WARN) at 125 °C and thermal shutdown (TCRIT) at 150 °C. Upon TCRIT detection, both buck channels disable immediately and nIRQ asserts low. Recovery requires removal of IC_EN signal or power cycle-no software intervention needed, ensuring fail-safe behavior in unattended systems.
DA9131-XXRT1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 24-PowerUFQFN
- Packaging:
- Tray
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.3V
- Voltage - Output (Max):
- 1.9V
- Current - Output:
- 10A
- Frequency - Switching:
- 4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
- 24-FCQFN (3.3x4.8)
DA9131-XXRT1 FAQ
1.How can I place an order for DA9131-XXRT1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DA9131-XXRT1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DA9131-XXRT1 reliable?
The price and inventory of DA9131-XXRT1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DA9131-XXRT1 is usually 5 days.
3.What payment methods are accepted for DA9131-XXRT1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DA9131-XXRT1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DA9131-XXRT1?
DA9131-XXRT1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DA9131-XXRT1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DA9131-XXRT1?
For technical support, including DA9131-XXRT1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DA9131-XXRT1 requirements.
6.How does Aetrix verify that DA9131-XXRT1 is sourced from the original manufacturer or authorized distributors?
All DA9131-XXRT1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DA9131-XXRT1 meets industry standards.
7.What is the process for return or replacement of DA9131-XXRT1?
All DA9131-XXRT1 units undergo pre-shipment inspection (PSI). If there is an issue with DA9131-XXRT1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DA9131-XXRT1 part is unused and in its original packaging.
Return procedure for DA9131-XXRT1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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