Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - DC DC Switching Regulators

Renesas DA9131-XXRT2

Name: DA9131-XXRT2
Brand: Renesas
SKU: DA9131-XXRT2
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: DA9131-XXRT2

Manufacturer:: Renesas

Category:: Voltage Regulators - DC DC Switching Regulators

Package:: 24-PowerUFQFN

Datasheet:: DA9131-XXRT2.pdf

Description:: IC REG BUCK ADJ 10A 24FCQFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,170

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

DA9131-XXRT2 from Renesas Electronics is a dual-channel, high-efficiency PMIC integrating two fully synchronous buck converters for CPU/GPU and DDR memory rail regulation in mobile and portable systems. It delivers up to 5 A per channel across 0.3 V–1.9 V output range from 2.8 V–5.5 V input, features I²C-compatible FM+ interface, remote sensing, and ±1 % static output voltage accuracy.

For engineers reviewing the DA9131-XXRT2 datasheet, DA9131-XXRT2 pinout, DA9131-XXRT2 application, or DA9131-XXRT2 equivalent, key selection considerations include its 24-pin FCQFN wettable-flank package, 4 MHz switching frequency, programmable soft-start, dynamic voltage control (DVC), and integrated thermal/overcurrent protection - all critical for compact, thermally constrained SoC power delivery designs.

Technical Context

The DA9131-XXRT2 implements two independent single-phase buck regulators with integrated high-side and low-side MOSFETs, eliminating external FETs or Schottky diodes. Each channel supports 4 MHz fixed-frequency PWM operation with adaptive phase selection and auto-mode efficiency optimization.

It employs precision remote-sense feedback (FB1P/FB1N and FB2P/FB2N) for ±1 % static output accuracy and includes dedicated GPIOs (GPIO0–GPIO4) configurable as inputs, outputs, or I²C bus pins (SCL/SDA), enabling flexible system-level control and multi-device addressing via CONF pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Voltage Range	2.8 V to 5.5 V - supports single-cell Li-ion, USB PD, and wide-input industrial rails without pre-regulation.
Output Voltage Range	0.3 V to 1.9 V in 10 mV steps - matches core voltage requirements of modern ARM CPUs, GPUs, and LPDDR4/5 memory.
Max Output Current	5 A per channel - sufficient for high-performance application processors and graphics subsystems.
Switching Frequency	4 MHz nominal - enables use of ultra-small 220 nH inductors and reduces output capacitor count (20 µF total per rail).
Output Accuracy	±1 % (static, VOUT ≥ 1 V) - ensures stable logic-level compliance and avoids timing margin violations in high-speed digital loads.
Protection Features	Integrated over-temperature, over-current, and power-good monitoring - eliminates need for external supervision ICs or discrete sense resistors.
Interface	I²C-compatible FM+ (1 MHz max) - supports fast register access for DVC, fault logging, and real-time rail adjustment.
Ambient Temp Range	−40 °C to +105 °C - qualified for extended-temperature consumer, industrial, and automotive-grade (DA9131-A) applications.

Pinout & Package

DA9131-XXRT2 is housed in a 24-pin FCQFN package (3.3 mm × 4.8 mm, wettable flanks), optimized for thermal performance and automated optical inspection (AOI) in high-density PCB layouts.

Pin/Terminal	Circuit Role	Design Meaning
PVDD1, PVDD2	Power supply input (Ch1/Ch2)	Dual independent input rails support split-bias or shared-input configurations; each rated for 5 A continuous current.
LX1, LX2	Buck switch node output	High-current analog outputs driving external 220 nH inductors; require low-inductance layout to minimize EMI and switching losses.
FB1P/FB1N, FB2P/FB2N	Differential remote sense inputs	Enable Kelvin connection to load point, maintaining ±1 % accuracy despite PCB trace IR drop under dynamic load transients.
SCL/GPIO3, SDA/GPIO4	I²C bus interface / configurable GPIO	FM+-compliant bidirectional lines allow daisy-chaining multiple DA9131-XXRT2 devices with unique slave addresses set via CONF pin.
IC_EN	Digital enable input	Active-high logic control enables/disables both buck channels simultaneously; supports sequencing with external power controllers.
PGND, AGND	Power and analog ground	Separate ground domains minimize noise coupling between switching and sensitive analog feedback paths.
CONF/GPIO0	Configuration select / GPIO	Hardware-selectable I²C address (0x48 or 0x49) and boot-time configuration mode; also usable as general-purpose input/output.

Key Features

Feature	Design Value
Dual independent buck regulators	Two fully integrated 5 A channels with separate feedback, enable, and sensing - enables independent voltage scaling for CPU and GPU/DDR rails.
Dynamic Voltage Control (DVC)	Real-time output adjustment via I²C register write or dedicated GPIO pin - reduces power consumption during low-load states without software intervention.
Programmable soft-start	Configurable ramp rate limits inrush current at power-up, preventing input rail collapse and ensuring clean system boot sequencing.
Wettable-flank FCQFN package	24-pin, 3.3 mm × 4.8 mm footprint with exposed thermal pad and solderable side walls - improves thermal transfer and enables AOI-compatible reflow inspection.
Integrated protection suite	On-die thermal shutdown, cycle-by-cycle current limiting, and power-good status reporting - eliminates external fault management circuitry.
Remote sensing architecture	Differential feedback (FBxP/FBxN) compensates for PCB voltage drop up to 100 mV - maintains tight regulation at point-of-load under 5 A transient steps.

Applications

Mobile Application Processors	LPDDR Memory Power
Use Scenario: Powering ARM-based application processors (e.g., Cortex-A78/A715 clusters) in smartphones and tablets requiring dynamic voltage/frequency scaling (DVFS). IC Role / Device Role / Timing Role: Dual-rail PMIC delivering independently controlled V_CORE (0.6–1.2 V) and V_GPU (0.7–1.3 V) with sub-10 µs DVC response time. Use Value: Enables precise, low-latency voltage transitions aligned with processor P-states - reducing active power by up to 30 % versus fixed-voltage solutions.	Use Scenario: Supplying LPDDR4/5 memory subsystems in portable computing devices where tight voltage tolerance and fast transient response are mandatory. IC Role / Device Role / Timing Role: Regulating VDDQ (1.1 V) and VDD2H (1.8 V) rails with ±1 % accuracy and <50 µs recovery from 3 A load steps. Use Value: Prevents data corruption during burst read/write operations by maintaining voltage within JEDEC-specified margins under 200 ns load transients.
SIPP Module Integration	Automotive Infotainment SoCs
Use Scenario: Embedded power solution for single-in-line pin package (SIPP) modules combining SoC, DRAM, and PMIC in a compact, board-level module. IC Role / Device Role / Timing Role: Primary DC-DC regulator providing V_SoC and V_DRAM with minimal external components (220 nH inductor + 20 µF ceramic caps per rail). Use Value: Reduces total solution area to 218 mm² - enabling ultra-thin module profiles while meeting IPC-7351B land pattern standards.	Use Scenario: Powering automotive-grade infotainment SoCs (e.g., Qualcomm SA8155P) in head units requiring AEC-Q100 Grade 2 compliance and extended temperature operation. IC Role / Device Role / Timing Role: Dual-rail regulator supporting V_CPU (0.8 V) and V_GPU (0.9 V) with −40 °C to +105 °C ambient rating and integrated thermal warning/fault signaling. Use Value: Eliminates need for external thermal sensors and discrete current monitors - simplifying ASIL-B relevant power architecture validation.

Mobile Application Processors

LPDDR Memory Power

Use Scenario: Powering ARM-based application processors (e.g., Cortex-A78/A715 clusters) in smartphones and tablets requiring dynamic voltage/frequency scaling (DVFS).

IC Role / Device Role / Timing Role: Dual-rail PMIC delivering independently controlled V_CORE (0.6–1.2 V) and V_GPU (0.7–1.3 V) with sub-10 µs DVC response time.

Use Value: Enables precise, low-latency voltage transitions aligned with processor P-states - reducing active power by up to 30 % versus fixed-voltage solutions.

Use Scenario: Supplying LPDDR4/5 memory subsystems in portable computing devices where tight voltage tolerance and fast transient response are mandatory.

IC Role / Device Role / Timing Role: Regulating VDDQ (1.1 V) and VDD2H (1.8 V) rails with ±1 % accuracy and <50 µs recovery from 3 A load steps.

Use Value: Prevents data corruption during burst read/write operations by maintaining voltage within JEDEC-specified margins under 200 ns load transients.

SIPP Module Integration

Automotive Infotainment SoCs

Use Scenario: Embedded power solution for single-in-line pin package (SIPP) modules combining SoC, DRAM, and PMIC in a compact, board-level module.

IC Role / Device Role / Timing Role: Primary DC-DC regulator providing V_SoC and V_DRAM with minimal external components (220 nH inductor + 20 µF ceramic caps per rail).

Use Value: Reduces total solution area to 218 mm² - enabling ultra-thin module profiles while meeting IPC-7351B land pattern standards.

Use Scenario: Powering automotive-grade infotainment SoCs (e.g., Qualcomm SA8155P) in head units requiring AEC-Q100 Grade 2 compliance and extended temperature operation.

IC Role / Device Role / Timing Role: Dual-rail regulator supporting V_CPU (0.8 V) and V_GPU (0.9 V) with −40 °C to +105 °C ambient rating and integrated thermal warning/fault signaling.

Use Value: Eliminates need for external thermal sensors and discrete current monitors - simplifying ASIL-B relevant power architecture validation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel buck PMIC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS65917B1RSLR	Single 5.5 V input, 3 buck + 5 LDOs; 2.5 MHz switching; no remote sensing; 0.6–1.52 V output range.	Targeted at TI Sitara AMx/AM6x SoCs; lacks differential feedback and DVC GPIO control.	Choose when multi-rail LDO integration is required alongside bucks, and remote sensing is not needed for load-point accuracy.
MPQ4572GQB-Z	Single-channel 5 A buck; 2.5–5.5 V input; 0.6–3.3 V output; no I²C interface; external compensation.	Used in cost-sensitive industrial HMIs; requires external FET drivers and feedback resistors.	Choose for simpler, lower-cost single-rail designs where digital control, dual-channel operation, and integrated protection are not required.

Compared with TPS65917B1RSLR and MPQ4572GQB-Z, the DA9131-XXRT2 uniquely combines dual 5 A buck channels, differential remote sensing, I²C-based DVC, and wettable-flank FCQFN packaging - making it optimal for space-constrained, high-accuracy, dynamically scaled SoC power delivery where layout density and thermal reliability are critical.

Availability

DA9131-XXRT2 is available at Aetrix Electronics and suitable for mobile processors, LPDDR memory subsystems, and SIPP module integration requiring stable component supply, long-term lifecycle support, and automotive-qualified variants.

Supply support for DA9131-XXRT2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog power management, and embedded solutions for automotive, industrial, and IoT markets.

The DA9131-XXRT2 belongs to Renesas' DA-series high-performance PMIC product line, engineered specifically for efficient, compact, and digitally controllable power delivery to advanced mobile and automotive SoCs.

FAQ

What is the maximum supported output current per channel for the DA9131-XXRT2?

The DA9131-XXRT2 supports up to 5 A continuous output current per buck channel under recommended operating conditions (T_A ≤ +105 °C, proper PCB thermal design). This rating is validated with 220 nH inductors and 20 µF output capacitance, and includes derating above 85 °C ambient per the power dissipation curve in the datasheet. The DA9131-XXRT2 integrates all power switches, so no external FETs are needed to achieve this current level.

Does the DA9131-XXRT2 support remote voltage sensing, and how is it implemented?

Yes, the DA9131-XXRT2 supports true differential remote sensing on both channels via dedicated FB1P/FB1N and FB2P/FB2N pins. This allows Kelvin connections directly at the load point, compensating for PCB trace resistance and maintaining ±1 % output voltage accuracy even under 5 A dynamic load steps. The DA9131-XXRT2 does not require external resistive dividers for basic operation - feedback is internally scaled and configured via I²C registers.

Can the DA9131-XXRT2 be used in automotive applications, and what qualification does it hold?

The DA9131-XXRT2 itself is rated for −40 °C to +105 °C ambient operation and meets industrial reliability standards. For automotive use, Renesas offers the pin- and function-compatible DA9131-A variant, which is AEC-Q100 Grade 2 qualified (−40 °C to +105 °C junction, HTOL tested). While the DA9131-XXRT2 shares identical electrical specs and package, only the DA9131-A carries formal automotive qualification - users targeting automotive ECUs must specify the -A suffix part number.

How does Dynamic Voltage Control (DVC) work on the DA9131-XXRT2?

Dynamic Voltage Control (DVC) on the DA9131-XXRT2 allows real-time adjustment of either buck output voltage in response to processor load changes. It can be triggered either by writing to the BUCK_BUCKx_0 register via I²C (supporting 10 mV steps), or by asserting a logic level on a dedicated GPIO pin (e.g., GPIO0 configured as DVC input). The DA9131-XXRT2 executes the transition with controlled slew rate to avoid overshoot, completing typical 100 mV steps in under 10 µs.

What package type and thermal characteristics does the DA9131-XXRT2 use?

The DA9131-XXRT2 uses a 24-pin FCQFN package measuring 3.3 mm × 4.8 mm with wettable flanks and an exposed thermal pad. Its thermal resistance is θ_JA = 21.21 °C/W (JEDEC 2S2P board), θ_JB = 12.37 °C/W, enabling >3 W total power dissipation with appropriate PCB copper area. The DA9131-XXRT2 includes on-die temperature monitoring with programmable warning and shutdown thresholds, reported via I²C status registers.

DA9131-XXRT2 Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: -

Package/Case:: 24-PowerUFQFN

Packaging:: Tape & Reel (TR)

Product Status:: Active

Function:: Step-Down

Output Configuration:: Positive

Topology:: Buck

Output Type:: Adjustable

Number of Outputs:: 1

Voltage - Input (Min):: 2.5V

Voltage - Input (Max):: 5.5V

Voltage - Output (Min/Fixed):: 0.3V

Voltage - Output (Max):: 1.9V

Current - Output:: 10A

Frequency - Switching:: 4MHz

Synchronous Rectifier:: Yes

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount, Wettable Flank

Supplier Device Package:: 24-FCQFN (3.3x4.8)

DA9131-XXRT2 FAQ

1.How can I place an order for DA9131-XXRT2 through Aetrix?

Please submit a Request for Quotation (RFQ) for DA9131-XXRT2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for DA9131-XXRT2 reliable?

The price and inventory of DA9131-XXRT2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DA9131-XXRT2 is usually 5 days.

3.What payment methods are accepted for DA9131-XXRT2?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DA9131-XXRT2 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for DA9131-XXRT2?

DA9131-XXRT2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your DA9131-XXRT2 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for DA9131-XXRT2?

For technical support, including DA9131-XXRT2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DA9131-XXRT2 requirements.

6.How does Aetrix verify that DA9131-XXRT2 is sourced from the original manufacturer or authorized distributors?

All DA9131-XXRT2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DA9131-XXRT2 meets industry standards.

7.What is the process for return or replacement of DA9131-XXRT2?

All DA9131-XXRT2 units undergo pre-shipment inspection (PSI). If there is an issue with DA9131-XXRT2, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The DA9131-XXRT2 part is unused and in its original packaging.

Return procedure for DA9131-XXRT2:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…