Renesas DA9220-70V72
- Part No.:
- DA9220-70V72
- Manufacturer:
- Renesas
- Package:
- 24-UFBGA, WLCSP
- Datasheet:
-
DA9220-70V72.pdf
- Description:
- IC REG BCK ADJ 3A/3A DL 24WLCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DA9220-70V72 from Renesas Electronics is a dual-channel synchronous buck DC-DC converter PMU delivering up to 3 A per channel at 0.3 V–1.9 V output, operating from 2.5 V–5.5 V input, with 4 MHz switching frequency and ±1 % static voltage accuracy. It integrates fully pass devices, supports remote sensing, and targets CPU/GPU/DDR power rails in space-constrained mobile SoC modules.
For engineers reviewing the DA9220-70V72 datasheet, DA9220-70V72 pinout, DA9220-70V72 application, or DA9220-70V72 equivalent, key selection criteria include dual-rail dynamic voltage control (DVC), I²C-compatible FM+ interface, 24WLCSP package compatibility, thermal warning/shutdown thresholds, and programmable soft-start slew rate for Li-ion battery-powered handheld systems.
Technical Context
The DA9220-70V72 implements two independent synchronous buck converters with integrated high-side PMOS (36 mΩ) and low-side NMOS (17 mΩ) switches, supporting PWM and auto-switching PFM modes. Each channel features differential remote-sense feedback (FB1P/FB1N, FB2P/FB2N), programmable current limit (8 A typical), and individually configurable DVC slew rates (10 mV per 0.5–8 µs).
Its digital control core includes an I²C FM+ interface (up to 1 MHz), six GPIOs (SCL/GPIO3, SDA/GPIO4, CONF/GPIO0, GPIO1, GPIO2, nIRQ), and register-mapped supervision of voltage, current, and temperature - with thermal warning (115–135 °C) and critical shutdown (130–150 °C) thresholds.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage | 2.5 V to 5.5 V - supports single-cell Li-ion (3.0–4.2 V) and fixed 3.3 V/5.0 V rails without external regulators. |
| Output Voltage Range | 0.3 V to 1.9 V in 10 mV steps - covers core logic (0.7–1.2 V), GPU (0.8–1.3 V), and DDR I/O (1.1–1.8 V) rails. |
| Max Output Current | 3 A per channel - sufficient for mid-tier application processors and LPDDR4 memory subsystems. |
| Switching Frequency | 4 MHz nominal - enables use of ultra-small 0.10 µH inductors and reduces output capacitor size. |
| Voltage Accuracy | ±1 % static (≥1 V), ±10 mV static (<1 V) - ensures stable operation of voltage-sensitive digital cores under load transients. |
| Thermal Protection | Thermal warning at 115–135 °C; shutdown at 130–150 °C - prevents damage during sustained high-load operation in sealed enclosures. |
| I²C Interface | FM+ compatible (up to 1 MHz) - allows fast configuration and real-time telemetry without bus contention in multi-PMU systems. |
Pinout & Package
DA9220-70V72 is housed in a 24-ball WLCSP package measuring 2.5 mm × 1.7 mm with 0.4 mm pitch, optimized for ultra-thin mobile PCBs and SIPP module integration.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PVDD1, PVDD2 | Power supply for Buck1/Buck2 power stages | Must be decoupled with 10 µF capacitors; shared with AVDD to minimize noise coupling into analog control circuitry. |
| LX1, LX2 | Buck switch nodes | Connect to 0.10 µH inductors; require tight layout to minimize EMI and switching losses; no external FETs needed. |
| FB1P/FB1N, FB2P/FB2N | Differential remote sense inputs | Enable point-of-load regulation by connecting FBxP to VOUTx and FBxN to local GND - eliminates IR drop errors across PCB traces. |
| SCL/GPIO3, SDA/GPIO4 | I²C clock/data or GPIO | Supports FM+ mode; internal pull-ups/pull-downs configurable; used for address selection and fault reporting via nIRQ. |
| IC_EN | Chip enable input | Active-high control: pulls down outputs and disables all blocks except POR when low - enables system-level power sequencing. |
| CONF/GPIO0 | Configuration select or GPIO | Determines I²C address (0x60–0x67) when used as CONF; allows up to eight DA9220-70V72 units on same bus without address conflict. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-channel DVC with programmable slew | Independent 10 mV/0.5–8 µs ramp control per buck - enables precise voltage scaling during CPU frequency transitions without overshoot. |
| Integrated power stage | No external MOSFETs or Schottky diodes required - reduces BOM count and layout area while maintaining 3 A capability per rail. |
| Remote differential sensing | FBxP/FBxN pairs eliminate trace IR drop impact - maintains ±1 % regulation accuracy even with 100+ mΩ PCB resistance between IC and SoC power pins. |
| Programmable soft-start | Configurable slew rate (e.g., 20 mV/µs) - limits inrush current from Li-ion battery during boot, preventing brownout in shared power domains. |
| Comprehensive supervision | Real-time monitoring of output voltage, current limit events, thermal warning/critical flags, and power-good status via I²C registers - enables autonomous system recovery. |
Applications
| Smartphone Application | Tablet PC Application |
|---|---|
|
Use Scenario: Powering application processor cores and GPU in a compact 6.5-inch smartphone with dual-SIM and 5G modem. IC Role / Device Role / Timing Role: Dual-rail PMU supplying VDD_CPU (0.85 V) and VDD_GPU (0.95 V) with synchronized DVC transitions during performance state changes. Use Value: Enables dynamic power scaling that reduces average SoC power by >25 % during video playback while maintaining ±1 % voltage stability under 5 A load transients. |
Use Scenario: Delivering regulated power to LPDDR4 memory and application SoC in a 10.1-inch Android tablet with active stylus support. IC Role / Device Role / Timing Role: Supplies VDD_DDR (1.1 V) and VDD_SOC (0.9 V) with remote sensing to compensate for 80 mΩ interconnect resistance between PMU and memory package. Use Value: Maintains DDR timing margin integrity by eliminating 45 mV IR drop error - prevents data corruption during burst read/write operations. |
| SIPP Module Application | Wi-Fi Module Application |
|
Use Scenario: Embedded power solution inside a 12 mm × 12 mm SIPP module integrating ARM Cortex-A53 SoC and 2 GB LPDDR3. IC Role / Device Role / Timing Role: Primary DC-DC regulator generating VDD_CORE (0.9 V) and VDD_IO (1.8 V) from 3.8 V battery input using ultra-compact 0.10 µH inductors. Use Value: Achieves 92 % peak efficiency at 1.5 A per rail while fitting within 2.5 mm × 1.7 mm footprint - maximizes module board area for RF shielding. |
Use Scenario: Power management for a M.2-form-factor Wi-Fi 6E module with dual-band RF transceivers and baseband processor. IC Role / Device Role / Timing Role: Supplies VDD_RF (1.3 V) and VDD_DIG (0.8 V) with fast load transient response (<15 mV deviation) during packet transmission bursts. Use Value: Limits voltage droop to <12 mV during 0→3 A step loads at 10 A/µs - prevents RF EVM degradation and packet loss in 802.11ax streams. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65218D0RSLR | Single-chip PMIC with 4 buck + 5 LDOs; lower max current (2 A/channel); 2.7–5.5 V input; no remote sensing. | Targets full-featured AM335x/AM437x-based industrial HMI; less suitable for high-accuracy mobile SoC rails. | Choose when needing mixed buck/LDO integration and lower cost, not when remote sensing or 3 A/channel is mandatory. |
| RTQ2132BGQW | 2-channel buck with 4 A/channel, 2.5–5.5 V input, but no I²C interface or DVC; only hardware-programmed voltages. | Used in cost-sensitive IoT gateways where firmware-controlled voltage scaling is unnecessary. | Choose for fixed-voltage, high-current applications without telemetry or adaptive scaling requirements. |
Compared with TPS65218D0RSLR and RTQ2132BGQW, DA9220-70V72 uniquely combines 3 A/channel capability, differential remote sensing, I²C-configurable DVC, and 24WLCSP packaging - making it the only option among the three qualified for precision voltage scaling in battery-powered SIPP modules.
Availability
DA9220-70V72 is available at Aetrix Electronics and suitable for smartphones, tablet PCs, and SIPP modules requiring stable component supply, long-term lifecycle support, and RoHS-compliant WLCSP packaging.
Supply support for DA9220-70V72 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog power management, and embedded solutions for automotive, industrial, and consumer markets.
The DA9220 product line was designed specifically for high-efficiency, space-constrained power delivery in mobile SoCs and SIPP modules - emphasizing low quiescent current, remote sensing accuracy, and firmware-controllable DVC.
FAQ
What is the maximum supported I²C clock frequency for DA9220-70V72?
The DA9220-70V72 supports Fast Mode Plus (FM+) I²C operation up to 1 MHz, enabling rapid register reads/writes for dynamic voltage control and real-time telemetry. This bandwidth allows full configuration of both buck channels-including DVC slew rate, output voltage, and protection thresholds-in under 200 µs, which is essential for responsive CPU DVFS in DA9220-70V72-based systems.
Does DA9220-70V72 require external MOSFETs or Schottky diodes?
No, DA9220-70V72 integrates fully synchronous power stages with 36 mΩ PMOS and 17 mΩ NMOS switches per channel, eliminating the need for external FETs or catch diodes. This integration reduces total solution size by >40 % compared to discrete buck controllers and ensures consistent thermal performance across voltage and load conditions in DA9220-70V72 deployments.
How does remote sensing work on DA9220-70V72, and what benefit does it provide?
DA9220-70V72 uses differential remote sense inputs (FB1P/FB1N and FB2P/FB2N) connected directly to the SoC's power pins and local ground. This measures voltage precisely at the load, rejecting IR drop errors from PCB traces. In practice, this maintains ±1 % regulation accuracy even with 100 mΩ routing resistance - a critical advantage for DA9220-70V72 in thin smartphone PCBs where trace resistance dominates.
What thermal protection features are implemented in DA9220-70V72?
DA9220-70V72 includes two-tier thermal protection: a warning flag asserted at 115–135 °C (configurable via register) and immediate buck shutdown at 130–150 °C. Both events generate I²C-accessible status bits (TEMP_WARN, TEMP_CRIT) and optional nIRQ interrupts. This dual threshold allows host firmware to throttle performance before shutdown - a key reliability feature for DA9220-70V72 in thermally constrained tablets and game consoles.
Can DA9220-70V72 support different output voltages for each channel simultaneously?
Yes, DA9220-70V72 independently programs VOUT1 (0.3–1.9 V) and VOUT2 (0.3–1.9 V) in 10 mV steps via I²C registers CH1_A_VOUT/CH2_A_VOUT. Each channel also stores a secondary "retention" voltage (CH1_B_VOUT/CH2_B_VOUT) for low-power states. Voltage selection is toggled dynamically using CH1_VSEL/CH2_VSEL bits - enabling asymmetric rail control essential for DA9220-70V72 in heterogeneous SoC architectures.
DA9220-70V72 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 24-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.3V
- Voltage - Output (Max):
- 1.9V
- Current - Output:
- 3A, 3A
- Frequency - Switching:
- 4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-WLCSP (2.48x1.68)
DA9220-70V72 FAQ
1.How can I place an order for DA9220-70V72 through Aetrix?
Please submit a Request for Quotation (RFQ) for DA9220-70V72 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DA9220-70V72 reliable?
The price and inventory of DA9220-70V72 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DA9220-70V72 is usually 5 days.
3.What payment methods are accepted for DA9220-70V72?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DA9220-70V72 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DA9220-70V72?
DA9220-70V72 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DA9220-70V72 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DA9220-70V72?
For technical support, including DA9220-70V72 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DA9220-70V72 requirements.
6.How does Aetrix verify that DA9220-70V72 is sourced from the original manufacturer or authorized distributors?
All DA9220-70V72 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DA9220-70V72 meets industry standards.
7.What is the process for return or replacement of DA9220-70V72?
All DA9220-70V72 units undergo pre-shipment inspection (PSI). If there is an issue with DA9220-70V72, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DA9220-70V72 part is unused and in its original packaging.
Return procedure for DA9220-70V72:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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