Analog Devices Inc. DAC8413EPZ
- Part No.:
- DAC8413EPZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- Digital to Analog Converters (DAC)
- Package:
- 28-DIP (0.600", 15.24mm)
- Datasheet:
-
DAC8413EPZ.pdf
- Description:
- IC DAC 12BIT V-OUT 28DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DAC8413EPZ from Analog Devices is a quad, 12-bit voltage-output DAC with readback capability, reset-to-zero functionality, and true buffered analog outputs. It operates from ±15 V or single +5 V supplies, supports unipolar/bipolar output ranges via VREFH/VREFL, and delivers 10 µs settling time to 0.01% with ±5 mA output drive-used in precision servo control and digitally calibrated instrumentation.
For engineers reviewing the DAC8413EPZ datasheet, DAC8413EPZ pinout, DAC8413EPZ application, or DAC8413EPZ equivalent, this page provides verified specifications, functional context for dual-supply and single-supply configurations, confirmed pin roles including R/W-controlled readback, and two validated alternative parts for design continuity in automatic test equipment and process control systems.
Technical Context
The DAC8413EPZ integrates four independent R-2R ladder DACs with high-impedance (50 kΩ) switching networks, each feeding a rail-to-rail output amplifier capable of sourcing/sinking ±5 mA. Its digital interface uses a 12-bit bidirectional bus with A0/A1 address decoding, active-low CS and LDAC, and asynchronous RESET that forces all output registers to 0x000.
Reference configuration is fully flexible: VREFH and VREFL set full-scale range without external resistors, enabling bipolar operation (e.g., ±10 V) or unipolar (0–10 V or –10–0 V). Readback is enabled only when VLOGIC = +5 V and R/W = HIGH, with data appearing on DB0–DB11 pins after CS assertion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit binary input (0x000 to 0xFFF), enabling 4096 discrete output levels. |
| Output Type | True buffered voltage output with integrated amplifiers-no external op-amp required for RL ≥ 2 kΩ, CL ≤ 100 pF. |
| Settling Time | 10 µs to 0.01% for 10 V step (±15 V supply); 7 µs for 2.5 V step (+5 V supply)-critical for fast waveform generation. |
| INL (E Grade) | ±0.25 LSB max (±15 V supply); ±0.5 LSB max (+5 V supply)-ensures monotonicity and calibration accuracy. |
| Supply Range | +5 V single supply or ±15 V dual supply; VLOGIC = +5 V required only for readback function. |
| Reference Inputs | VREFH and VREFL define output span (e.g., VREFH = +10 V, VREFL = –10 V → ±10 V output); code-dependent input currents require buffering for VREFH. |
| Readback Support | Yes-bidirectional DB0–DB11 bus reads previously loaded data when R/W = HIGH, CS = LOW, and VLOGIC = +5 V. |
Pinout & Package
Package: 28-lead plastic DIP (PDIP), 0.6-inch width, through-hole mounting. Pin 1 identified by notch or dot; pin 1 corner marked on top view.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 VREFH | High-side reference input | Sinks/sources code-dependent current; sets upper output limit-must be buffered if reference lacks sink capability. |
| 2 VOUTB | DAC B analog output | Buffered voltage output with ±5 mA drive; short-circuit protected; no external amplifier needed for typical loads. |
| 3 VOUTA | DAC A analog output | Identical to VOUTB-enables independent control of four analog channels from one IC. |
| 4 VSS | Negative power supply rail | Accepts –15 V to 0 V; defines lower supply boundary for analog section and reference circuitry. |
| 5 DGND | Digital ground reference | Separate from analog ground-requires star grounding at single point to minimize noise coupling. |
| 6 RESET | Asynchronous reset input | Active-low signal forcing all output registers to 0x000 (DAC8413EPZ behavior); operates independently of CS. |
| 7 LDAC | Load DAC input | Active-low latch controlling simultaneous update of all four DAC output registers-enables synchronized channel updates. |
| 8–19 DB0–DB11 | Bidirectional data bus | 12-bit parallel interface: DB0 (LSB) to DB11 (MSB); functions as input during write, output during readback. |
| 20 R/W | Read/write control | LOW = write data to selected DAC register; HIGH = enable readback of selected register onto DB0–DB11. |
| 21 A1, 22 A0 | Address select inputs | Binary-encoded selection of DAC A (00), B (01), C (10), or D (11); decoded only when CS = LOW. |
| 23 CS | Chip select | Active-low enable for address decoding, register access, and bus direction control-required for all operations. |
| 24 VLOGIC | Readback logic supply | +5 V required only for readback; open-circuit if unused-does not power internal logic or DAC core. |
| 25 VDD | Positive power supply rail | +5 V to +15 V operation; powers analog core, references, and output amplifiers. |
| 26 VOUTD | DAC D analog output | Fourth independent buffered output-supports multi-channel closed-loop control without additional DACs. |
| 27 VOUTC | DAC C analog output | Matches VOUTA/VOUTB performance-guaranteed ±1 LSB linearity matching between adjacent DACs. |
| 28 VREFL | Low-side reference input | Current-sink only (0 to –2.75 mA); sets lower output limit-no buffering required. |
Key Features
| Feature | Design Value |
|---|---|
| Quad DAC integration | Four independent 12-bit DACs in one 28-pin PDIP-reduces board space and interconnect complexity vs. discrete solutions. |
| Reset-to-zero architecture | RESET pin forces all output registers to 0x000 (DAC8413EPZ), ensuring known startup state for safety-critical servo applications. |
| Flexible reference configuration | VREFH/VREFL directly define output range (e.g., 0–2.5 V, ±5 V, –10–+10 V) without resistor networks-improves temperature stability over offset-based methods. |
| Double-buffered inputs | Separate input and output registers allow asynchronous loading and synchronized updating-prevents partial updates during multi-DAC control. |
| Readback capability | Verified data integrity via DB0–DB11 readout-enables firmware validation of loaded values without external ADC monitoring. |
| Single +5 V operation | Full functionality (including 2.5 V output swing) with only +5 V and GND-simplifies power design in embedded systems. |
Applications
| Automatic Test Equipment (ATE) | Digitally Controlled Calibration |
|---|---|
Use Scenario: Generating precise stimulus voltages for DUT biasing and parameter sweeps across temperature and voltage corners. IC Role / Device Role / Timing Role: Quad voltage source providing synchronized, programmable DC offsets and ramp waveforms to multiple DUT pins. Use Value: 12-bit resolution and ±0.25 LSB INL ensure measurement repeatability; readback confirms loaded codes before test execution. |
Use Scenario: Adjusting gain/offset trim points in sensor signal chains and power supply feedback loops during factory calibration. IC Role / Device Role / Timing Role: Precision analog output generator delivering stable reference voltages to op-amp summing nodes or DAC reference inputs. Use Value: Buffered outputs drive calibration potentiometers or reference dividers directly; reset-to-zero ensures consistent zero-point initialization. |
| Servo Control Systems | Process Control Equipment |
Use Scenario: Closed-loop position/velocity control in industrial actuators using four independent analog command signals. IC Role / Device Role / Timing Role: Real-time analog command generator interfacing with motor driver ICs or analog PID controllers. Use Value: 10 µs settling time enables kHz-bandwidth control loops; LDAC synchronization prevents phase skew across axes. |
Use Scenario: Multi-channel analog setpoint generation for temperature, pressure, and flow controllers in PLC I/O modules. IC Role / Device Role / Timing Role: Field-programmable analog output module supporting HART-compatible 4–20 mA loop drivers or direct voltage interfaces. Use Value: ±15 V operation supports legacy 0–10 V industrial standards; VREFH/VREFL flexibility allows adaptation to diverse sensor ranges. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 12-bit voltage-output DAC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5724RBRUZ | 12-bit, quad, SPI interface; integrated reference; no readback; ±10.5 V output swing; 10 µs settling. | Requires SPI host controller instead of parallel bus; lacks readback verification; better suited for space-constrained designs. | Select AD5724RBRUZ when serial interface and smaller footprint (24-lead TSSOP) outweigh need for parallel bus and readback. |
| DAC8564IPW | 16-bit, quad, SPI interface; internal 2.5 V reference; no readback; 10 µs settling; ±10 V output with external op-amps. | Higher resolution but requires external amplification for full-scale output; no native readback or reset-to-zero. | Select DAC8564IPW when 16-bit precision is mandatory and system already uses SPI peripherals-accept trade-off of added external components. |
Compared with DAC8413EPZ, AD5724RBRUZ offers modern serial control and integrated reference but removes parallel bus compatibility and readback; DAC8564IPW adds resolution but increases BOM count and eliminates hardware reset assurance-DAC8413EPZ remains optimal for legacy parallel-bus systems requiring deterministic initialization and code verification.
Availability
DAC8413EPZ is available at Aetrix Electronics and suitable for automatic test equipment, digitally controlled calibration, and servo control systems requiring stable component supply, long-term obsolescence management, and MIL-STD-883 qualified variants.
Supply support for DAC8413EPZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, founded in 1965 and headquartered in Wilmington, MA.
The DAC8412/DAC8413 family was designed for precision industrial control and instrumentation applications requiring quad-channel voltage synthesis, robust power supply flexibility, and hardware-level readback verification-targeting systems where deterministic reset behavior and analog output integrity are critical.
FAQ
What is the key functional difference between DAC8413EPZ and DAC8412EPZ?
The DAC8413EPZ resets all output registers to minimum scale (0x000) upon assertion of the active-low RESET pin, while the DAC8412EPZ resets to midscale (0x800). This distinction makes DAC8413EPZ ideal for unipolar systems requiring guaranteed zero-voltage startup, such as 0–10 V process control outputs. Both share identical pinout, timing, and electrical specifications otherwise.
Does DAC8413EPZ require external op-amps to drive standard 2 kΩ loads?
No. DAC8413EPZ includes fully buffered voltage outputs capable of sourcing and sinking ±5 mA into RL = 2 kΩ with CL ≤ 100 pF, meeting 0.01% settling in 10 µs under ±15 V supplies. External amplification is unnecessary unless driving capacitive loads >100 pF or resistive loads <2 kΩ.
Can DAC8413EPZ operate from a single +5 V supply, and what output range is achievable?
Yes. With VDD = +5 V, VSS = GND, VREFH = +2.5 V, and VREFL = 0 V, DAC8413EPZ delivers a 0–2.5 V unipolar output range. Full functionality-including readback (with VLOGIC = +5 V), double-buffering, and RESET-is retained. Power dissipation drops to 60 mW in this configuration.
How does the readback feature of DAC8413EPZ work, and what conditions must be met?
DAC8413EPZ readback requires VLOGIC = +5 V, CS = LOW, R/W = HIGH, and valid A0/A1 addressing. When enabled, previously loaded data appears on DB0–DB11 within tCSD (320 ns max). This allows firmware to verify correct register loading without external measurement-critical for safety-critical calibration sequences.
What is the maximum recommended load capacitance for stable operation of DAC8413EPZ outputs?
DAC8413EPZ is characterized for CL ≤ 100 pF with RL = 2 kΩ. Exceeding 100 pF may degrade settling time and increase overshoot. For higher capacitance loads (e.g., cable-driven systems), an external unity-gain buffer is recommended-verified performance data is not provided beyond 100 pF in the datasheet.
DAC8413EPZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-DIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Number of Bits:
- 12
- Number of D/A Converters:
- 4
- Settling Time:
- 10µs (Typ)
- Output Type:
- Voltage - Buffered
- Differential Output:
- No
- Data Interface:
- Parallel
- Reference Type:
- External
- Voltage - Supply, Analog:
- 5V ~ 15V, -15V
- Voltage - Supply, Digital:
- 5V
- INL/DNL (LSB):
- ±0.25, -1
- Architecture:
- R-2R
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 28-PDIP
- Mounting Type:
- Through Hole
- Grade:
- -
- Qualification:
- -
DAC8413EPZ FAQ
1.How can I place an order for DAC8413EPZ through Aetrix?
Please submit a Request for Quotation (RFQ) for DAC8413EPZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DAC8413EPZ reliable?
The price and inventory of DAC8413EPZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DAC8413EPZ is usually 5 days.
3.What payment methods are accepted for DAC8413EPZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DAC8413EPZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DAC8413EPZ?
DAC8413EPZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DAC8413EPZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DAC8413EPZ?
For technical support, including DAC8413EPZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DAC8413EPZ requirements.
6.How does Aetrix verify that DAC8413EPZ is sourced from the original manufacturer or authorized distributors?
All DAC8413EPZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DAC8413EPZ meets industry standards.
7.What is the process for return or replacement of DAC8413EPZ?
All DAC8413EPZ units undergo pre-shipment inspection (PSI). If there is an issue with DAC8413EPZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DAC8413EPZ part is unused and in its original packaging.
Return procedure for DAC8413EPZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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