Texas Instruments DAC8740HRGET
- Part No.:
- DAC8740HRGET
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
DAC8740HRGET.pdf
- Description:
- IC INTERFACE SPECIALIZED 24VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:760
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Product details
Overview
DAC8740HRGET from Texas Instruments is a HART® and FOUNDATION Fieldbus™/PROFIBUS PA dual-mode physical layer modem IC designed for industrial process automation transmitters. It integrates UART digital interface, 1200/2200-Hz FSK modulation/demodulation, Manchester encoder/decoder, internal 1.5-V reference, and programmable band-pass filter - enabling single-chip fieldbus communication in 4-mm × 4-mm VQFN-24 packages.
For engineers reviewing the DAC8740HRGET datasheet, DAC8740HRGET pinout, DAC8740HRGET application, or DAC8740HRGET equivalent, this page delivers verified technical context, real-world timing behavior (e.g., carrier start/stop times), supply current profiles across HART/FF modes, clocking options (internal oscillator, crystal, CMOS), and precise pin-level functional mapping for system integration and layout validation.
Technical Context
The DAC8740HRGET implements a half-duplex HART physical layer with integrated transmit modulator (1200 Hz mark / 2200 Hz space), receive demodulator, and configurable internal band-pass filter (BPF_EN controlled). It supports both slave and master configurations with minimal external filtering components.
In FOUNDATION Fieldbus H1 mode, it functions as a complete MAU and controller with 31.25 kbit/s Manchester encoding/decoding, jabber inhibition, and carrier detect logic - fully compliant with IEC 61158-2 and IEC 61784-1 standards for FF and PROFIBUS PA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| HART FSK Frequencies | 1200 Hz (mark) and 2200 Hz (space); frequency error ±1% over –40°C to +105°C ensures reliable HART signal recognition. |
| FF/PA Bit Rate | 31.25 kbit/s ±0.2% tolerance; meets IEC 61158-2 timing requirements for Manchester-coded bus-powered communication. |
| Supply Current (HART Mode) | 180 µA max at –40°C to +85°C with external clock; enables ultra-low-power operation in battery-backed or loop-powered transmitters. |
| Internal Reference | 1.5 V ±2% (1.47–1.53 V); low-load-regulation (1.3 V/mA) supports stable analog signal conditioning without external reference. |
| Operating Temperature | –55°C to +125°C junction; validated for harsh industrial environments including oil & gas downhole and chemical plant installations. |
| Digital Interface | UART (RX/TX/RTS/CD pins); no SPI support - distinct from DAC8741H; simplifies microcontroller integration in legacy HART systems. |
| Package | VQFN-24 (RGE), 4 mm × 4 mm, 0.5-mm pitch; thermal pad improves power dissipation in sealed transmitter housings. |
Pinout & Package
VQFN-24 (RGE) package with exposed thermal pad (connected to GND). 4-mm × 4-mm footprint, 0.5-mm lead pitch, and 0.8-mm nominal height enable compact placement on 4-layer industrial PCBs with thermal vias under the pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XEN | Digital input | Crystal oscillator enable; low = enable external crystal (1.2288/3.6864 MHz); high = disable crystal, select internal oscillator or CMOS clock. |
| UART_IN | Digital input | HART UART data input; accepts 1200-baud asynchronous frames from host MCU; VIH ≥ 0.7×IOVDD ensures robust noise immunity. |
| UART_RTS | Digital input/output | Request-to-send control; high = enable demodulator/disabled modulator; low = enable modulator/disabled demodulator - defines HART half-duplex direction. |
| CD | Digital output | Carrier detect; logic high indicates valid HART carrier presence (≥80 mVPP) or FF/PA carrier lock - used for automatic mode switching. |
| MOD_OUT | Analog output | FSK sinusoid (HART) or Manchester waveform (FF/PA); requires 5–22 nF AC-coupling cap in HART mode; drives 160-Ω load directly. |
| REF_EN | Digital input | Reference enable; high = activate internal 1.5-V reference; low = disable internal ref and accept external 2.5-V source on REF pin. |
| BPF_EN | Digital input | Band-pass filter enable; high = engage internal filter (680 pF on MOD_INF for HART); eliminates need for external LC filters. |
Key Features
| Feature | Design Value |
|---|---|
| HART + FF/PA dual-mode compliance | Fully satisfies HART 7.5 physical layer spec and IEC 61158-2 FF H1/PROFIBUS PA requirements in one device - reduces BOM count and qualification effort. |
| Integrated clock generation | Supports internal oscillator (1.2288 MHz), external crystal (1.2288/3.6864 MHz), or CMOS clock - eliminates external timing IC and saves board space. |
| Low-quiescent-current design | 180 µA max in HART mode at industrial temp range; enables >10-year battery life in wireless HART sensors or extended loop-powered operation. |
| Internal 1.5-V voltage reference | 1.5 V ±2%, 1.3 V/mA load regulation; powers internal DAC and analog blocks - removes need for external precision reference in cost-sensitive designs. |
| Configurable band-pass filtering | On-chip BPF (enabled via BPF_EN) with fixed 680-pF MOD_INF connection for HART - reduces external component count by up to 6 passive parts per channel. |
Applications
| HART Field Transmitter | FOUNDATION Fieldbus H1 Device |
|---|---|
Use Scenario: 4–20 mA smart pressure transmitter with HART digital overlay in refinery process lines. IC Role / Device Role / Timing Role: Physical layer modem handling HART FSK modulation/demodulation, carrier detection, and UART framing between sensor MCU and 4–20 mA loop. Use Value: Enables remote configuration, diagnostics, and multi-variable readout over legacy analog infrastructure without adding external modems or level shifters. |
Use Scenario: Distributed temperature sensor node on FOUNDATION Fieldbus network in chemical plant DCS. IC Role / Device Role / Timing Role: MAU and H1 controller executing Manchester encoding/decoding, jabber control, and carrier synchronization at 31.25 kbit/s. Use Value: Provides native FF compliance with <100 µs jitter tolerance and guaranteed 31.25 kbit/s timing - eliminates need for external PHY or FPGA-based protocol stacks. |
| PROFIBUS PA Actuator Interface | Hybrid Loop-Powered Sensor |
Use Scenario: Smart valve positioner communicating via PROFIBUS PA in hazardous area Zone 1. IC Role / Device Role / Timing Role: Dual-mode modem operating in PROFIBUS PA mode (identical electrical layer to FF H1), managing Manchester data stream and bus power management. Use Value: Single-chip solution certified for intrinsic safety applications; supports bus-powered operation with <200 µA quiescent current in decode-active state. |
Use Scenario: Battery-assisted wireless HART sensor that falls back to wired 4–20 mA + HART during maintenance or low-SNR conditions. IC Role / Device Role / Timing Role: Reconfigurable modem switching between UART-based HART and internal oscillator clocking to minimize active power draw. Use Value: Extends battery life by >3× vs discrete modem solutions through integrated low-leakage regulators and power-down mode (<60 µA). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fieldbus modem applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DAC8741HRGET | SPI interface instead of UART; includes CRC checking and watchdog timer; same pinout but different digital I/O mapping (SDI/SDO/SCLK/IRQ vs UART_IN/UART_OUT/UART_RTS/CD). | Required when host MCU uses SPI-only peripherals or needs daisy-chain capability; not drop-in replaceable due to interface and interrupt logic differences. | Select DAC8741HRGET only if SPI integration, FIFO buffering, or enhanced reliability features (CRC/watchdog) are required - UART-based systems must retain DAC8740HRGET. |
| AD5700-1ACPZ-RL7 | HART-only modem (no FF/PA support); 16-pin LFCSP; lacks internal reference and integrated BPF; requires external crystal and reference. | Applicable only for pure HART implementations where FF/PA compatibility is unnecessary; higher external component count and larger PCB footprint. | Choose AD5700-1 only for cost-optimized, HART-only designs with available board space for external filters and references - DAC8740HRGET provides broader protocol coverage in same footprint. |
Compared with DAC8741HRGET, DAC8740HRGET offers simpler UART integration and lower software overhead but lacks SPI flexibility and CRC protection; versus AD5700-1, it delivers dual-protocol support, integrated reference, and reduced external parts - making it optimal for next-gen hybrid field devices requiring HART + FF/PA interoperability.
Availability
DAC8740HRGET is available at Aetrix Electronics and suitable for industrial process control, PLC I/O modules, and field transmitter designs requiring stable component supply, long-term lifecycle assurance, and full HART/FF/PA certification documentation.
Supply support for DAC8740HRGET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies for industrial, automotive, and communications markets.
The DAC8740HRGET belongs to TI's industrial communications portfolio, engineered specifically to consolidate HART, FOUNDATION Fieldbus, and PROFIBUS PA physical layers into a single, low-power, qualification-ready modem IC for smart field instrumentation.
FAQ
What communication protocols does the DAC8740HRGET support?
The DAC8740HRGET supports HART 7.5 physical layer (1200/2200 Hz FSK), FOUNDATION Fieldbus H1 (31.25 kbit/s Manchester), and PROFIBUS PA (electrically identical to FF H1). It does not support HART 5, HART 6, or other variants - only the specified dual-mode operation per SBAS856D datasheet revision D. All three protocols share the same MOD_OUT/MOD_IN analog path and internal clocking architecture.
Does DAC8740HRGET include an internal voltage reference?
Yes, DAC8740HRGET integrates a precision 1.5-V internal reference with ±2% accuracy (1.47–1.53 V) and 1.3 V/mA load regulation. When REF_EN is high, the internal reference is enabled and appears on the REF pin; when REF_EN is low, REF becomes an input for an external 2.5-V reference. This eliminates need for external reference ICs in most HART/FF transmitter designs.
What are the clocking options supported by DAC8740HRGET?
DAC8740HRGET supports three clock sources: internal oscillator (1.2288 MHz), external crystal (1.2288 MHz or 3.6864 MHz), or external CMOS clock. Clock selection is controlled via CLK_CFG0/CLK_CFG1 pins and XEN pin state. The internal oscillator requires no external components, while crystal mode needs 16-pF or 36-pF load capacitors on X1/X2 pins - all options are validated across –55°C to +125°C.
Can DAC8740HRGET operate in both HART and FOUNDATION Fieldbus modes simultaneously?
No, DAC8740HRGET operates in one mode at a time - either HART or FOUNDATION Fieldbus/PROFIBUS PA - selected by firmware configuration of internal registers. Mode switching requires reinitialization of the modem block, clock tree, and filter settings. Simultaneous dual-mode operation is not supported; the device shares analog front-end resources and cannot generate or decode both FSK and Manchester signals concurrently.
What is the function of the BPF_EN pin on DAC8740HRGET?
BPF_EN is a digital input that enables or disables the internal band-pass filter. When high, the internal BPF engages - requiring a 680-pF capacitor on MOD_INF for HART mode or 120-pF for FF/PA mode. When low, the internal filter is bypassed and an external filter must be used. This pin directly controls analog signal path routing and must be driven to a defined logic level; floating is not allowed.
DAC8740HRGET Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- -
- Interface:
- UART
- Voltage - Supply:
- 1.71V ~ 5.5V
- Supplier Device Package:
- 24-VQFN (4x4)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DAC8740HRGET FAQ
1.How can I place an order for DAC8740HRGET through Aetrix?
Please submit a Request for Quotation (RFQ) for DAC8740HRGET on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DAC8740HRGET reliable?
The price and inventory of DAC8740HRGET are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DAC8740HRGET is usually 5 days.
3.What payment methods are accepted for DAC8740HRGET?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DAC8740HRGET transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DAC8740HRGET?
DAC8740HRGET orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DAC8740HRGET order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DAC8740HRGET?
For technical support, including DAC8740HRGET datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DAC8740HRGET requirements.
6.How does Aetrix verify that DAC8740HRGET is sourced from the original manufacturer or authorized distributors?
All DAC8740HRGET products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DAC8740HRGET meets industry standards.
7.What is the process for return or replacement of DAC8740HRGET?
All DAC8740HRGET units undergo pre-shipment inspection (PSI). If there is an issue with DAC8740HRGET, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DAC8740HRGET part is unused and in its original packaging.
Return procedure for DAC8740HRGET:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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