Analog Devices Inc. DC1058A-C

Overview

DC1058A-C from Analog Devices (formerly Linear Technology) is a high-performance 16-bit, 105Msps analog-to-digital converter optimized for undersampling wideband RF signals up to 700MHz full-power bandwidth. It features 78.2dBFS noise floor, 100dB spurious-free dynamic range (SFDR), and ultralow 80fsRMS aperture jitter-enabling high-fidelity digitization in cellular base station receivers and spectrum analyzers.

For engineers reviewing the DC1058A-C datasheet, DC1058A-C pinout, DC1058A-C application, or DC1058A-C equivalent, this page delivers verified technical context, validated pin functions, confirmed AC/DC specifications, and real-world deployment guidance for demanding communications signal chain design.

Technical Context

The DC1058A-C implements a 16-bit pipelined ADC architecture with integrated PGA front end, supporting dual input ranges (2.25VP-P or 1.5VP-P) via the PGA pin. Its sample-and-hold stage achieves 700MHz full-power bandwidth and 80fsRMS jitter, enabling clean undersampling of IF/RF signals without external anti-alias filtering.

It uses differential LVDS/PECL/TTL/CMOS clock inputs (ENC+/ENC–), supports optional internal dither and data randomization, and provides programmable output format (offset binary or 2's complement) and clock duty cycle stabilization-ensuring robust timing integrity across varied system clock sources.

Key Specifications

Pinout & Package

DC1058A-C is housed in a 48-pin 7mm × 7mm plastic QFN package with exposed thermal pad (Pin 49 = GND). The package supports high-frequency layout integrity via dedicated analog/digital ground separation, low-inductance power bypassing (0.1μF per VDD pin), and differential input/output routing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9268BCPZ-105, DC1058A-C integrates reference, PGA, and duty-cycle stabilization-reducing component count and layout risk. Against LTC2206CUK#PBF, it delivers 31% higher sample rate and 25mW higher power for extended undersampling capability.

Availability

DC1058A-C is available at Aetrix Electronics and suitable for cellular infrastructure, test instrumentation, and medical imaging systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for DC1058A-C includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and RF ICs, serving communications, industrial, automotive, and healthcare markets.

The DC1058A-C belongs to the LTC220x family of ultra-low-jitter, wideband ADCs designed specifically for demanding communications signal chains-including direct RF sampling, broadband test equipment, and high-fidelity imaging front ends.

FAQ

What is the maximum analog input frequency supported by the DC1058A-C?

The DC1058A-C supports a full-power analog input bandwidth of 700MHz, enabling undersampling of RF signals far beyond its 105Msps Nyquist limit. This allows direct digitization of UHF bands (e.g., 450–700MHz) without analog downconversion-preserving signal integrity and simplifying receiver architecture. Performance remains characterized up to 250MHz with ≥90dB SFDR and ≥73dB SNR.

Does the DC1058A-C require an external reference voltage?

No-the DC1058A-C includes an internal 2.5V bandgap reference. Connecting the SENSE pin to VDD activates it, setting a full-scale range of 2.25VP-P (PGA = 0). An external 1.25V or 2.5V reference may be used instead, but the internal reference eliminates BOM cost and improves startup stability. The VCM pin provides a buffered 1.25V common-mode output essential for differential input biasing.

How does the PGA pin affect the DC1058A-C's input range and dynamic range?

The PGA pin selects between two front-end gains: low = 1× (2.25VP-P full-scale input range), high = 1.5× (1.5VP-P full-scale). At 1.5× gain, the input voltage swing is reduced but system sensitivity increases-improving SNR for low-amplitude signals. Both configurations maintain the same 100dB SFDR and 78.2dBFS noise floor, allowing dynamic range optimization per signal chain requirement without hardware change.

Can the DC1058A-C operate with a single-ended clock input?

Yes-the ENC+ and ENC– inputs accept single-ended drive (e.g., TTL, CMOS, or sine wave) with ENC– bypassed to ground via 0.1μF. Internal 1.6V bias resistors ensure proper common-mode level. However, differential clocking (LVDS/PECL) is recommended for lowest jitter and best SFDR performance. The optional clock duty cycle stabilizer further relaxes timing constraints when using asymmetric clocks.

What is the purpose of the RAND pin on the DC1058A-C?

The RAND pin enables digital output randomization: when high, D1–D15 are XORed with D0 (LSB), scrambling the parallel data pattern. This reduces deterministic electromagnetic interference (EMI) from repetitive bus transitions-critical in sensitive RF environments like base station radios. The original data is recovered by reapplying the same XOR operation externally, adding negligible latency with no impact on timing margins.