Analog Devices Inc. DC1369A-A

Overview

LTC2261-14 from Analog Devices (formerly Linear Technology) is a 14-bit, 125Msps ultralow-power analog-to-digital converter optimized for undersampling high-frequency IF signals in communications infrastructure. It delivers 73.4dB SNR, 85dB SFDR, and 0.17psRMS aperture jitter with single 1.8V supply, CMOS/DDR-CMOS/DDR-LVDS output options, and 800MHz full-power bandwidth - enabling direct digitization of 70MHz cellular and SDR waveforms.

For engineers reviewing the LTC2261-14 datasheet, LTC2261-14 pinout, LTC2261-14 application, or LTC2261-14 equivalent, this page provides verified specifications, validated pin functions across all output modes, real-world performance data at 125Msps, confirmed alternatives for 14-bit ADC migration, and design-critical guidance on reference configuration, clock duty cycle stabilization, and power mode selection.

Technical Context

The LTC2261-14 employs a pipelined ADC architecture with integrated sample-and-hold, correction logic, and configurable digital output drivers. Its ENC+/ENC– differential clock interface supports sine, PECL, LVDS, TTL, or CMOS inputs, and the optional clock duty cycle stabilizer maintains performance across wide duty cycle ranges without external circuitry.

Digital outputs are selectable between full-rate CMOS, double-data-rate CMOS, and double-data-rate LVDS - each with independent OVDD supply (1.2V–1.9V for CMOS; 1.7V–1.9V for LVDS). The SPI port enables runtime configuration of randomizer, nap/sleep modes, and input range via PAR/SER-controlled serial or parallel programming.

Key Specifications

Pinout & Package

40-lead (6mm × 6mm) plastic QFN package (UJ), exposed pad soldered to PCB ground. Pin numbering follows standard top-view layout with GND (Pin 41) as exposed thermal pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9246BCPZ-125, the LTC2261-14 offers lower system-level power and integrated clock conditioning at slight SNR trade-off; versus LTC2260-14, it delivers 20Msps higher throughput with only 22mW additional dissipation - making it optimal for next-generation SDR and 5G FR1 IF digitization.

Availability

LTC2261-14 is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio, portable medical imaging, multi-channel data acquisition, and nondestructive testing requiring stable component supply and long-term production continuity.

Supply support for LTC2261-14 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and DSP technologies, serving industrial, automotive, communications, and healthcare markets.

The LTC2261-14 belongs to Linear's ultralow-power, high-speed ADC product line designed specifically for undersampling RF/IF signals in communications and instrumentation - emphasizing jitter performance, power efficiency, and flexible digital interfacing.

FAQ

What is the maximum sampling rate supported by the LTC2261-14?

The LTC2261-14 supports a maximum sampling rate of 125Msps, validated across temperature and process corners. This rate is specified with differential ENC+/ENC– clock input, 2VP-P analog input range, and 1.8V supplies. At 125Msps, the LTC2261-14 achieves 73.4dB SNR and 85dB SFDR at 70MHz input frequency, confirming its suitability for demanding IF sampling applications.

Does the LTC2261-14 require an external reference, or does it include an internal one?

The LTC2261-14 includes a precision internal reference (VREF = 1.25V ±2.5%) and supports both internal and external reference configurations. When SENSE (Pin 39) is tied to VDD, the internal reference is selected with ±1V input range; grounding SENSE selects ±0.5V range. An external reference (0.625V–1.3V) can be applied directly to SENSE for custom scaling - the LTC2261-14 uses this voltage to set full-scale range without additional components.

How does the clock duty cycle stabilizer function in the LTC2261-14?

The LTC2261-14's optional clock duty cycle stabilizer corrects asymmetrical ENC+/ENC– waveforms to maintain timing accuracy. Enabled via CS pin in parallel programming mode, it operates independently of sampling rate and preserves 73.4dB SNR even with 20%–80% duty cycle inputs. This eliminates the need for external clock dividers or delay-locked loops in FPGA-based systems where clock tree skew is difficult to control.

What digital output interfaces does the LTC2261-14 support, and how are they configured?

The LTC2261-14 supports three digital output modes: full-rate CMOS, double-data-rate CMOS, and double-data-rate LVDS - selected via SCK pin in parallel mode or SPI register in serial mode. CMOS outputs operate from 1.2V–1.8V OVDD; LVDS outputs use 1.8V OVDD with programmable 1.75mA/3.5mA current. All modes share identical D0–D13 pin assignments, enabling hardware reuse across interface choices.

Is the LTC2261-14 pin-compatible with other devices in the same family?

Yes, the LTC2261-14 is pin-compatible and register-compatible with the LTC2260-14 (105Msps) and LTC2259-14 (80Msps) within the same 40-pin QFN (6mm × 6mm) UJ package. This allows drop-in replacement across speed grades without PCB redesign, facilitating scalable system development and inventory rationalization - all three share identical pin functions, power domains, and SPI configuration structure.