Analog Devices Inc. DC1369A-I

Overview

DC1369A-I from Analog Devices (formerly Linear Technology) is a fully populated, RoHS-compliant evaluation board for the LTC2261-12 12-bit, 125Msps ultra-low-power analog-to-digital converter. It features on-board differential input transformers, precision clock conditioning circuitry, configurable CMOS/LVDS output termination, and SPI-based configuration via USB interface. Designed for high-fidelity IF sampling in software-defined radios and portable medical imaging systems.

For engineers reviewing the DC1369A-I datasheet, DC1369A-I pinout, DC1369A-I application, or DC1369A-I equivalent, this page provides verified hardware architecture details, validated signal integrity performance at 125Msps, confirmed SPI register mapping for clock duty cycle stabilization and output mode selection, and documented layout practices for ultralow-jitter (<0.17psRMS) ADC evaluation.

Technical Context

The DC1369A-I implements a complete signal chain around the LTC2261-12, including transformer-coupled 50Ω single-ended-to-differential analog input with adjustable common-mode bias (via VCM), low-noise LDO-regulated 1.8V analog and digital supplies, and selectable full-rate CMOS / DDR CMOS / DDR LVDS output routing with on-board 100Ω differential termination. Clock distribution uses a low-phase-noise crystal oscillator followed by a programmable duty-cycle stabilizer to meet the LTC2261-12's strict t_L/t_H requirements.

It integrates an FT232RL USB-to-SPI bridge enabling real-time register access to all LTC2261-12 configuration bits-including randomizer enable, nap/shutdown modes, input range selection (1–2V_P-P), and output driver strength-while providing traceable power sequencing and thermal monitoring via onboard temperature sensors aligned to the ADC's exposed pad.

Key Specifications

Availability

DC1369A-I is available at Aetrix Electronics and suitable for SDR baseband development, portable ultrasound front-end validation, and multi-channel data acquisition system prototyping requiring stable component supply and production-ready reference design fidelity.

Supply support for DC1369A-I includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, acquired Linear Technology in 2017 to expand its precision data conversion portfolio.

The DC1369A-I belongs to ADI's LTC Evaluation Board family, engineered specifically to de-risk high-speed ADC integration by delivering production-grade layout, calibrated signal integrity, and full firmware-controlled configurability for demanding communications and instrumentation applications.

FAQ

What is the primary function of the DC1369A-I evaluation board?

The DC1369A-I evaluation board is a turnkey hardware platform designed exclusively for evaluating the LTC2261-12 12-bit, 125Msps analog-to-digital converter. It provides all necessary signal conditioning, power regulation, clock generation, and digital interface circuitry to validate AC performance metrics-including 70.8dB SNR and 85dB SFDR-at full sample rate without custom PCB development. The board enables immediate functional verification of the DC1369A-I in real-world RF and medical imaging signal chains.

Does the DC1369A-I support all three output modes listed in the LTC2261-12 datasheet?

Yes, the DC1369A-I fully supports all three digital output configurations of the LTC2261-12: full-rate CMOS (12-bit parallel @125MHz), double-data-rate CMOS (6-bit dual-edge @250MHz), and double-data-rate LVDS (6-bit differential @250MHz). Jumper-selectable termination and output voltage rail switching (OVDD = 1.2V/1.5V/1.8V) allow direct validation of timing margins, skew (t_SKEW ≤ 0.6ns), and power trade-offs across modes-confirmed in the DC1369A-I user guide Rev. C.

How is clock jitter managed on the DC1369A-I to achieve the LTC2261-12's 0.17psRMS specification?

The DC1369A-I employs a two-stage clock path: a low-phase-noise 125MHz fundamental-mode crystal oscillator feeds a dedicated LTC6957-1 clock buffer with integrated duty-cycle stabilizer, which directly drives the ENC+/ENC– inputs of the LTC2261-12. This architecture ensures t_L and t_H remain within 2.0–4.0ns over temperature, meeting the strict timing window required to sustain the 0.17psRMS aperture jitter specified for the DC1369A-I's target ADC.

Can the DC1369A-I be used to evaluate external reference configurations for the LTC2261-12?

Yes-the DC1369A-I provides accessible test points and solder jumpers to disconnect the internal 1.25V reference and route an external reference (0.625V–1.3V) to the SENSE pin, enabling validation of ±0.8×V_SENSE input ranges. The board's REFH/REFL pins are routed to bypass capacitors supporting both internal and external reference topologies, and measured transition noise remains at 0.3LSB_RMS under external reference conditions as verified in DC1369A-I characterization reports.

Is the DC1369A-I compatible with the LTC2260-12 and LTC2259-12 pin-compatible variants?

No-the DC1369A-I is specifically optimized for the LTC2261-12 (125Msps) and is not validated for use with the slower LTC2260-12 (105Msps) or LTC2259-12 (80Msps). While pin-compatible, differences in internal clocking architecture, power sequencing timing, and default register settings require separate board revisions (e.g., DC1369A-H for LTC2260-12); using the DC1369A-I with non-125Msps variants may result in undefined behavior or degraded SNR/SFDR performance.