Analog Devices Inc. DC1370A-A

Overview

LTC2261-14 from Analog Devices (formerly Linear Technology) is a 14-bit, 125Msps ultralow-power analog-to-digital converter optimized for undersampling high-frequency IF signals in communications infrastructure. It delivers 73.4dB SNR, 85dB SFDR, and 0.17psRMS aperture jitter with single 1.8V supply, CMOS/DDR-CMOS/DDR-LVDS outputs, and 800MHz full-power bandwidth - enabling direct digitization of 70MHz cellular and SDR waveforms.

For engineers reviewing the LTC2261-14 datasheet, LTC2261-14 pinout, LTC2261-14 application, or LTC2261-14 equivalent, key selection criteria include its 125Msps sampling rate at 127mW power, differential input support up to 2VP-P, SPI-configurable modes (randomizer, duty cycle stabilizer), and QFN-40 package compatibility across the LTC226x-14 family.

Technical Context

The LTC2261-14 employs a 14-bit pipelined ADC architecture with integrated sample-and-hold, correction logic, and configurable output drivers. Its 0.17psRMS jitter enables clean undersampling of 70–140MHz IF bands without external clock cleanup, while the dual-reference system (internal 1.25V VREF or external 0.625–1.3V on SENSE) supports ±0.5V to ±1V input ranges.

Digital interface flexibility includes three output modes: full-rate CMOS (14 parallel bits), DDR-CMOS (7-bit double-data-rate), or DDR-LVDS (7 differential pairs), each selectable via PAR/SER and SCK pins. The SPI port (CS/SCK/SDI/SDO) provides real-time configuration of randomization, nap/sleep modes, and clock duty cycle stabilization - critical for deterministic timing in multi-channel base station receivers.

Key Specifications

Pinout & Package

40-lead (6mm × 6mm) plastic QFN package (UJ) with exposed thermal pad (Pin 41 = GND). Pin functions are consistent across output modes except for data pins (D0–D13, OF, CLKOUT±, D*_+, D*_-).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9246BCPZ-125 and LTC2260-14, the LTC2261-14 uniquely balances 125Msps speed, flexible digital outputs, and on-chip configurability - making it optimal for space-constrained, multi-standard wireless platforms where layout reuse and firmware adaptability are critical.

Availability

LTC2261-14 is available at Aetrix Electronics and suitable for cellular base stations, software defined radios, portable medical imaging, and nondestructive testing requiring stable component supply across extended temperature ranges (–40°C to 85°C).

Supply support for LTC2261-14 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving communications, industrial, automotive, and healthcare markets.

The LTC2261-14 belongs to ADI's high-speed data converter product line, designed specifically for demanding communications infrastructure applications requiring ultralow jitter, wide dynamic range, and flexible digital interfacing in compact packages.

FAQ

What is the maximum analog input frequency supported by the LTC2261-14?

The LTC2261-14 features an 800MHz full-power bandwidth, allowing it to accurately digitize analog signals up to 800MHz without significant amplitude roll-off. This enables direct undersampling of IF signals in the 70–140MHz range commonly used in cellular base stations and SDRs, provided the Nyquist criterion is met for the chosen sampling rate.

Does the LTC2261-14 support both internal and external voltage references?

Yes, the LTC2261-14 supports both internal and external references. Connecting the SENSE pin to VDD selects the internal 1.25V reference with ±1V input range; connecting SENSE to GND selects ±0.5V range. An external reference between 0.625V and 1.3V can also be applied directly to the SENSE pin for custom scaling, with corresponding VREF output tracking.

How does the clock duty cycle stabilizer function in the LTC2261-14?

The LTC2261-14's clock duty cycle stabilizer corrects asymmetric encode clock waveforms, maintaining timing margins when the ENC+/ENC– duty cycle deviates from 50%. Enabled via CS pin in parallel mode, it operates across the full 1–125MHz sampling range and eliminates the need for external clock conditioning circuits in noisy environments.

What digital output interface options are available on the LTC2261-14?

The LTC2261-14 offers three configurable digital output interfaces: full-rate CMOS (14 single-ended bits), double-data-rate CMOS (7-bit DDR), or double-data-rate LVDS (7 differential pairs). Mode selection is controlled by PAR/SER and SCK pins, and OVDD voltage sets output swing (1.2–1.8V for CMOS, 1.7–1.9V for LVDS).

Is the LTC2261-14 pin-compatible with other members of the LTC226x-14 family?

Yes, the LTC2261-14 is fully pin-compatible with the LTC2260-14 (105Msps) and LTC2259-14 (80Msps), sharing identical 40-pin QFN packaging, pin functions, and SPI register map. This allows hardware reuse across performance tiers while maintaining firmware compatibility for configuration and monitoring.