Analog Devices Inc. DC1370A-B

Overview

LTC2261-14 from Analog Devices (formerly Linear Technology) is a 14-bit, 125Msps ultralow-power analog-to-digital converter optimized for high-frequency signal digitization in communications infrastructure. It delivers 73.4dB SNR, 85dB SFDR, and 0.17psRMS jitter at 1.8V supply, enabling undersampling of IF signals up to 140MHz in cellular base stations and software-defined radios.

For engineers reviewing the LTC2261-14 datasheet, LTC2261-14 pinout, LTC2261-14 application, or LTC2261-14 equivalent, key selection criteria include its 800MHz full-power bandwidth, selectable CMOS/LVDS DDR outputs, 1.8V single-supply operation, and SPI-configurable clock duty cycle stabilizer and output randomizer - all in a 40-pin 6mm × 6mm QFN package.

Technical Context

The LTC2261-14 employs a pipelined ADC architecture with integrated sample-and-hold, correction logic, and configurable digital output drivers. Its analog front-end supports differential input ranges from 1VP-P to 2VP-P and features 800MHz full-power bandwidth with ±1LSB INL and ±0.3LSB DNL over temperature.

Digital interface flexibility includes full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS outputs, each with independent OVDD supply (1.2V–1.8V for CMOS; 1.7V–1.9V for LVDS). Clock inputs accept differential (ENC+/ENC–) or single-ended drive, with optional duty cycle stabilization for robust timing at full speed.

Key Specifications

Pinout & Package

40-lead (6mm × 6mm) plastic QFN package (UJ), exposed pad soldered to PCB ground for thermal and electrical performance. Pin 41 is exposed pad (GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with LTC2261-14, AD9246BCPZ-125 offers superior SFDR and modern serialization but demands JESD204B infrastructure, while LTC2260-14 provides identical form-factor and feature set at lower speed and power - making it a seamless performance-downgrade option without PCB changes.

Availability

LTC2261-14 is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio development, and portable medical imaging systems requiring stable component supply and long-term production continuity.

Supply support for LTC2261-14 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving communications, industrial, automotive, and healthcare markets.

The LTC2261-14 belongs to ADI's high-speed precision ADC product line, designed specifically for demanding RF/IF digitization in wireless infrastructure and instrumentation where dynamic range, low jitter, and power efficiency are critical.

FAQ

What is the maximum analog input frequency supported by the LTC2261-14?

The LTC2261-14 features an 800MHz full-power bandwidth, allowing it to accurately digitize analog signals up to that frequency without significant amplitude roll-off. This enables direct undersampling of IF signals in the 70–140MHz range commonly used in cellular base stations and SDRs, provided the Nyquist criterion is met for the chosen sampling rate (125Msps).

Does the LTC2261-14 support both internal and external voltage references?

Yes, the LTC2261-14 supports both internal and external references. The SENSE pin configures the internal reference: tied to VDD for ±1V input range, or to GND for ±0.5V range. An external reference between 0.625V and 1.3V can also be applied directly to the SENSE pin, enabling custom full-scale calibration and improved system-level accuracy.

How does the clock duty cycle stabilizer function in the LTC2261-14?

The LTC2261-14's optional clock duty cycle stabilizer corrects asymmetric encode clocks, maintaining high AC performance even with duty cycles from 20% to 80%. Enabled via the CS pin in parallel programming mode, it eliminates the need for external clock conditioners - reducing BOM cost and PCB area while ensuring consistent aperture jitter and SNR at full 125Msps operation.

What digital output formats are available on the LTC2261-14?

The LTC2261-14 supports three digital output configurations: full-rate CMOS (125MHz parallel bus), double-data-rate CMOS (62.5MHz clock with two data edges), and double-data-rate LVDS (62.5MHz clock with differential signaling). Output mode is selected via the SCK pin in parallel mode or SPI register in serial mode, with OVDD setting voltage levels or current drive strength.

Is the LTC2261-14 pin-compatible with other devices in its family?

Yes, the LTC2261-14 is pin-compatible with the LTC2260-14 (105Msps) and LTC2259-14 (80Msps), sharing identical 40-pin 6mm × 6mm QFN packaging, pin functions, and register map. This allows hardware reuse across performance tiers - for example, designing a single PCB that supports all three speeds via firmware configuration and BOM variation.