Analog Devices Inc. DC1370A-I

Overview

LTC2261-12 from Analog Devices (formerly Linear Technology) is a 12-bit, 125Msps ultralow-power analog-to-digital converter optimized for high-frequency signal digitization in communications systems. It delivers 70.8dB SNR, 85dB SFDR, and 0.17psRMS jitter, operating from a single 1.8V supply with CMOS, DDR CMOS, or DDR LVDS outputs in a 40-pin QFN package. It serves as the front-end ADC in cellular base stations and software-defined radios.

For engineers reviewing the LTC2261-12 datasheet, LTC2261-12 pinout, LTC2261-12 application, or LTC2261-12 equivalent, key selection criteria include its 125Msps sampling rate at 124mW power, 800MHz full-power bandwidth, ±0.3LSB INL, and configurable input range (1–2VP-P) - all critical for IF undersampling and wideband receiver design.

Technical Context

The LTC2261-12 employs a 12-bit pipelined ADC core with integrated sample-and-hold, correction logic, and programmable output drivers. Its ENC+/ENC– differential clock interface supports sine, PECL, LVDS, TTL, or CMOS inputs, and an optional duty cycle stabilizer maintains performance across non-50% clock duty cycles.

Digital outputs are configurable via PAR/SER pin: serial SPI mode enables full register control (including randomizer and nap/shutdown), while parallel mode uses CS/SCK/SDI for simplified configuration. Output supply OVDD (1.2–1.8V for CMOS; 1.7–1.9V for LVDS) decouples digital swing from analog rail, enabling mixed-voltage system interfacing.

Key Specifications

Pinout & Package

40-lead (6mm × 6mm) plastic QFN package (UJ), exposed pad soldered to PCB ground for thermal and electrical integrity. Pin 41 is exposed pad (GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9226BCPZ-65, the LTC2261-12 offers 92% higher sampling rate and LVDS/DDR flexibility; compared with LTC2260-12, it provides 19% higher throughput at only 20% higher power - making it optimal for next-generation wideband receivers where speed and spectral purity are paramount.

Availability

LTC2261-12 is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio development, and portable medical imaging requiring stable component supply across long production lifecycles.

Supply support for LTC2261-12 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.

The LTC2261-12 belongs to ADI's high-speed precision ADC product line, designed specifically for wideband communications and instrumentation applications demanding ultralow jitter, high SNR, and flexible digital interfacing.

FAQ

What is the maximum sampling rate supported by the LTC2261-12?

The LTC2261-12 supports a maximum sampling rate of 125Msps, validated across the full industrial temperature range (–40°C to +85°C). This rate is specified under conditions of 1.8V VDD, sine-wave ENC input, and 2VP-P differential analog input. At this rate, the LTC2261-12 maintains 70.8dB SNR and 85dB SFDR, confirming its suitability for high-frequency undersampling applications such as cellular base station IF digitization.

Does the LTC2261-12 support both internal and external voltage references?

Yes, the LTC2261-12 supports both internal and external references via the SENSE pin. When SENSE is tied to VDD, the internal reference configures a ±1V input range; when grounded, it selects ±0.5V. Applying an external voltage between 0.625V and 1.3V to SENSE sets the input range to ±0.8×VSENSE. The internal reference provides 1.25V ±2.5% with ±25ppm/°C drift, eliminating external components in many applications.

Can the LTC2261-12 operate with a 1.2V OVDD supply in CMOS output mode?

Yes, the LTC2261-12 supports OVDD from 1.1V to 1.9V in CMOS output modes. At OVDD = 1.2V, VOH is guaranteed ≥1.185V and VOL ≤0.010V under 500µA load, enabling direct interfacing with 1.2V FPGA I/O banks. This rail flexibility reduces system-level voltage translation requirements and simplifies power domain partitioning in mixed-signal designs using the LTC2261-12.

How does the clock duty cycle stabilizer function in the LTC2261-12?

The LTC2261-12's clock duty cycle stabilizer corrects non-50% ENC+/ENC– duty cycles to maintain timing accuracy and minimize aperture jitter. Enabled via CS pin (high in parallel mode), it operates independently of sampling rate and input frequency. When active, tL and tH are stabilized to 2.0–4.76ns (min–max) across temperature, ensuring consistent setup/hold margins for reliable data capture - especially critical when using PLL-derived clocks with variable duty cycles.

Is the LTC2261-12 pin-compatible with other members of the LTC226x family?

Yes, the LTC2261-12 is pin-compatible with the LTC2260-12 (105Msps) and LTC2259-12 (80Msps) within the same UJ 40-pin QFN package. All share identical pinout, register map, and feature set - differing only in maximum sampling rate and corresponding power consumption. This allows hardware reuse across performance tiers: a single PCB can support all three variants via firmware configuration and BOM selection.