Analog Devices Inc. DC1370A-J

Overview

DC1370A-J from Analog Devices (formerly Linear Technology) is an evaluation board designed to demonstrate the LTC2258-12, a 12-bit, 65 Msps ultralow-power analog-to-digital converter with 71.1 dB SNR, 88 dB SFDR, and 0.17 psRMS jitter. It supports CMOS, DDR CMOS, and DDR LVDS output modes and targets high-frequency signal digitization in communications infrastructure.

For engineers reviewing the DC1370A-J datasheet, DC1370A-J pinout, DC1370A-J application, or DC1370A-J equivalent, this page provides verified hardware configuration details, supported ADC operating modes, interface compatibility (SPI, differential clock, parallel/serial programming), power sequencing requirements, and layout-critical design considerations for RF-sampling applications.

Technical Context

The DC1370A-J implements the LTC2258-12 in its full 65 Msps capability with on-board differential analog input conditioning, selectable 1.2 V / 1.5 V / 1.8 V OVDD supply, and configurable ENC+/ENC– clock termination. It integrates a precision 2.2 µF + 0.1 µF REFH/REFL bypass network and supports both internal (±1 V) and external reference configurations via the SENSE pin.

Board-level features include a dedicated SPI interface (CS/SCK/SDI/SDO) for register configuration, jumper-selectable output mode (full-rate CMOS, DDR CMOS, DDR LVDS), and exposed thermal pad soldering for optimal thermal performance. The design adheres to high-speed ADC layout best practices including controlled-impedance traces, ground plane integrity, and analog/digital domain separation.

Key Specifications

Availability

DC1370A-J is available at Aetrix Electronics and suitable for cellular base station development, software-defined radio prototyping, portable medical imaging systems, and multi-channel data acquisition requiring stable component supply and validated high-speed ADC evaluation platforms.

Supply support for DC1370A-J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors.

The DC1370A-J belongs to Analog Devices' high-speed ADC evaluation platform family, engineered specifically to accelerate time-to-test for RF-sampling applications demanding sub-0.2 psRMS jitter, wide full-power bandwidth (>800 MHz), and flexible digital interface options.

FAQ

What is the primary function of the DC1370A-J evaluation board?

The DC1370A-J evaluation board is a fully assembled and tested platform for the LTC2258-12 12-bit, 65 Msps analog-to-digital converter. Its purpose is to enable rapid characterization of AC performance (SNR, SFDR, jitter), validation of digital interface timing (CMOS/LVDS), and system-level integration testing - all without requiring custom PCB design. The DC1370A-J includes calibrated analog input circuitry, configurable power domains, and SPI-based register control to exercise all key features of the LTC2258-12.

Which ADC variants does the DC1370A-J support besides the LTC2258-12?

The DC1370A-J is specifically optimized for the LTC2258-12 but maintains mechanical and electrical compatibility with the pin-compatible LTC2257-12 (40 Msps) and LTC2256-12 (25 Msps) due to identical 40-lead (6 mm × 6 mm) QFN packaging and shared register map. All three devices use the same footprint, power architecture, and SPI command set, allowing the DC1370A-J to evaluate performance trade-offs across sample rates without hardware modification.

How is the analog input range configured on the DC1370A-J?

The DC1370A-J supports three analog input ranges via the SENSE pin connection: ±1 V (SENSE tied to VDD), ±0.5 V (SENSE tied to GND), or ±0.8 × V_SENSE (external reference applied to SENSE between 0.625 V and 1.3 V). The board provides test points and solder jumpers to configure SENSE, and the input path is AC-coupled with 50 Ω impedance matching - enabling direct connection to signal generators or RF sources without external baluns for differential drive.

Does the DC1370A-J support DDR LVDS output mode, and what are the implementation requirements?

Yes, the DC1370A-J supports DDR LVDS output mode via jumper configuration (JP1–JP3) and requires OVDD = 1.8 V with internal 100 Ω differential termination enabled. The board routes D[0_1]± through D[10_11]± to 100 Ω edge-mounted SMA connectors, and CLKOUT± is provided separately. Proper termination at the receiving end (100 Ω differential load) is mandatory to meet the specified 247–454 mV differential output voltage and maintain signal integrity at 65 Msps DDR data rates.

What power supply requirements must be met to operate the DC1370A-J at full 65 Msps performance?

To achieve full 65 Msps operation with specified AC performance (71.1 dB SNR, 88 dB SFDR), the DC1370A-J requires clean, low-noise 1.8 V for VDD (analog supply), 1.8 V for OVDD (LVDS mode) or 1.2 V/1.5 V/1.8 V (CMOS modes), and proper decoupling: 0.1 µF ceramic capacitors on every VDD/OGND/OVDD pair plus 2.2 µF ceramics on REFH/REFL. Power sequencing is not required, but simultaneous ramp-up of VDD and OVDD within 100 ms is recommended to avoid latch-up or initialization faults in the LTC2258-12.