Analog Devices Inc. DC1525B-D

Overview

LTC2172-14 from Analog Devices (formerly Linear Technology) is a 14-bit, 65 Msps quad-channel simultaneous-sampling analog-to-digital converter optimized for high-dynamic-range RF/IF digitization. It delivers 73.7 dB SNR, 90 dB SFDR, and 0.15 psRMS aperture jitter, enabling undersampling of 70–140 MHz IF signals in cellular base stations and software-defined radios.

For engineers reviewing the LTC2172-14 datasheet, LTC2172-14 pinout, LTC2172-14 application, or LTC2172-14 equivalent, key selection criteria include its 4-channel synchronization capability, serial LVDS output architecture (1- or 2-lane), 1.8 V single-supply operation, and support for differential or single-ended clock inputs with internal duty-cycle stabilization.

Technical Context

The LTC2172-14 integrates four independent 14-bit ADC cores with a shared sample-and-hold front-end offering 800 MHz full-power bandwidth. Its digital interface uses serialized LVDS outputs per channel-configurable for 1-bit or 2-bit per lane-with programmable output current (1.75 mA or 3.5 mA) and on-chip 100 Ω termination.

It supports flexible reference configuration via the SENSE pin (internal ±0.5 V / ±1 V or external 0.625–1.3 V), and includes SPI-compatible serial programming (via CS/SCK/SDI/SDO) and parallel mode control (via PAR/SER). Clock input accepts differential (LVDS/PECL) or single-ended (CMOS/TTL) signals with internal duty-cycle correction.

Key Specifications

Pinout & Package

Package: 52-lead (7 mm × 8 mm) plastic QFN with exposed thermal pad (Pin 53 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-channel, 14-bit ADC applications.

Compared with AD9257BSTZ-65 and LTC2262CUK#PBF, the LTC2172-14 uniquely combines quad-channel simultaneity, embedded LVDS serialization, and sub-0.2 psRMS jitter in a single 52-pin QFN - reducing component count, PCB area, and timing alignment effort in space-constrained RF systems.

Availability

LTC2172-14 is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio, portable medical imaging, and multichannel test equipment requiring stable component supply and long-term obsolescence management.

Supply support for LTC2172-14 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving aerospace, communications, industrial, and healthcare markets.

The LTC2172-14 belongs to ADI's high-speed data converter product line, designed specifically for demanding RF/IF digitization where simultaneous multi-channel sampling, low jitter, and compact serial interfaces are essential.

FAQ

What is the maximum input frequency supported by the LTC2172-14?

The LTC2172-14 features an 800 MHz full-power bandwidth sample-and-hold amplifier, allowing it to accurately digitize analog inputs up to 800 MHz in undersampling applications. Performance metrics such as 73.7 dB SNR and 90 dB SFDR are specified up to 140 MHz input frequency at 65 Msps, confirming robust wideband operation well beyond the Nyquist limit.

Does the LTC2172-14 support both internal and external voltage references?

Yes, the LTC2172-14 supports flexible reference configuration via the SENSE pin. Tying SENSE to VDD selects the internal reference with ±1 V input range; grounding SENSE selects ±0.5 V range; applying 0.625–1.3 V externally sets an input range of ±0.8 × VSENSE. The internal reference provides 1.25 V ±25 ppm/°C drift, and external reference mode maintains ±1 LSB INL accuracy.

How many LVDS data lanes does the LTC2172-14 use per channel, and how is it configured?

The LTC2172-14 supports two LVDS serialization modes per channel: 1-lane (one bit per clock edge) or 2-lane (two bits per clock edge). Mode selection is controlled by the CS pin in parallel programming mode (PAR/SER = VDD) or via SPI register write in serial mode. 2-lane mode reduces required LVDS clock frequency by half, easing timing closure on FPGAs with limited I/O speed.

What is the pipeline latency of the LTC2172-14, and why does it matter?

The LTC2172-14 has a fixed pipeline latency of 6 clock cycles from encode edge to first valid serialized output bit. This deterministic delay is critical for time-sensitive closed-loop systems (e.g., digital predistortion in transmitters) where precise alignment between ADC samples and DAC updates is required. The latency remains constant across all sample rates and serialization modes.

Can the LTC2172-14 operate with a single-ended clock input?

Yes, the LTC2172-14 supports single-ended clock operation: tie ENC– to GND and drive ENC+ with a 1.8 V square wave (VIH ≥ 1.2 V, VIL ≤ 0.6 V). Internal circuitry converts the single-ended signal into a pseudo-differential pair. However, differential clocking (LVDS/PECL) is recommended for optimal jitter performance and noise immunity, especially above 30 MHz.