Analog Devices Inc. DC1532A-C

Overview

LTC2268-14 from Analog Devices (formerly Linear Technology) is a 14-bit, dual-channel, simultaneous-sampling analog-to-digital converter optimized for high-frequency signal digitization in communications infrastructure. It delivers 73.1dB SNR, 88dB SFDR, and ultralow 0.15ps_RMS aperture jitter at 125Msps sampling rate, enabling undersampling of IF signals up to 140MHz with exceptional noise performance in cellular base station receivers.

For engineers reviewing the LTC2268-14 datasheet, LTC2268-14 pinout, LTC2268-14 application, or LTC2268-14 equivalent, key selection criteria include its 40-pin QFN package, serial LVDS output architecture (1- or 2-lane per channel), 1.8V single-supply operation, ±1LSB INL, and support for differential or single-ended encode clock inputs - all critical for RF receiver front-end and software-defined radio designs.

Technical Context

The LTC2268-14 integrates two independent 14-bit ADC cores with shared PLL-based clock conditioning and a duty-cycle stabilizer, enabling full-speed performance across wide input clock duty cycles (20%–80%). Its sample-and-hold features 800MHz full-power bandwidth and supports selectable 1V_P-P to 2V_P-P differential input ranges via SENSE pin configuration.

Digital interface uses serialized LVDS outputs with programmable 1.75mA/3.5mA drive strength and optional internal 100Ω termination. Configuration is handled via SPI port (serial mode) or parallel logic inputs (parallel mode), supporting shutdown and nap modes for dynamic power management in multichannel systems.

Key Specifications

Pinout & Package

40-lead (6mm × 6mm) plastic QFN package with exposed pad (Pin 41 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, high-speed ADC applications.

Compared with AD9250BCPZ-14 and ADS42JB69IRGCT, the LTC2268-14 offers superior jitter performance (0.15ps_RMS vs ≥0.25ps) and integrated clock conditioning - reducing external component count and improving IF undersampling margin in compact RF receivers.

Availability

LTC2268-14 is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio, and portable medical imaging applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for LTC2268-14 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving aerospace, communications, industrial, and healthcare markets.

The LTC2268-14 belongs to ADI's high-speed precision ADC product line, engineered specifically for RF receiver front-ends where low jitter, high SFDR, and dual-channel simultaneity are mandatory for modern wireless standards.

FAQ

What is the maximum input frequency supported by the LTC2268-14?

The LTC2268-14 features an 800MHz full-power bandwidth, allowing it to accurately digitize analog input signals up to 800MHz without significant amplitude roll-off. In practice, its usable Nyquist zone extends to 140MHz for high-SNR applications at 125Msps sampling, validated by FFT measurements showing 73.1dB SNR and 88dB SFDR at that frequency. The device supports undersampling architectures for IF frequencies beyond baseband.

Does the LTC2268-14 require an external reference voltage?

No - the LTC2268-14 includes an internal reference and supports three reference configurations via the SENSE pin: connecting SENSE to VDD selects ±1V input range with internal reference; grounding SENSE selects ±0.5V range; applying 0.625V–1.3V to SENSE configures ±0.8×V_SENSE range. External references are optional and only needed when higher accuracy or custom range is required.

How does the LTC2268-14 handle clock duty-cycle variation?

The LTC2268-14 incorporates an internal clock duty-cycle stabilizer that maintains full AC performance (73.1dB SNR, 88dB SFDR) across input clock duty cycles from 20% to 80%. This eliminates the need for external duty-cycle correction circuits, simplifying clock generation in systems using crystal oscillators, PLLs, or FPGA-derived clocks with inherent asymmetry.

What are the power consumption modes of the LTC2268-14?

The LTC2268-14 offers three operational power states: active mode (299mW at 125Msps, 2-lane), nap mode (70mW), and sleep mode (1mW). Nap mode retains register settings and allows fast wake-up (<1µs), while sleep mode powers down all circuitry except basic bias. These modes are controlled via SPI or parallel logic inputs (CS/SDI), enabling dynamic power scaling in battery-powered or thermally constrained systems.

Can the LTC2268-14 be configured for single-ended clock input?

Yes - the ENC+ and ENC– inputs support both differential and single-ended operation. In single-ended mode, ENC– is tied to GND and ENC+ accepts TTL, CMOS, or 1.8V square-wave signals. The datasheet specifies VIH = 1.2V and VIL = 0.6V for ENC+ under 1.8V VDD, ensuring compatibility with standard logic families without level-shifting circuitry.