Analog Devices Inc. DC1532A-G

Overview

LTC2268-12 from Analog Devices (formerly Linear Technology) is a 12-bit, dual-channel, simultaneous-sampling analog-to-digital converter optimized for high-frequency communications signal digitization. It delivers 70.6dB SNR, 88dB SFDR, and ultralow 0.15ps_RMS aperture jitter at 125Msps sampling rate, with serial LVDS outputs and single 1.8V supply operation - ideal for cellular base station IF receivers and software-defined radio front ends.

For engineers reviewing the LTC2268-12 datasheet, LTC2268-12 pinout, LTC2268-12 application, or LTC2268-12 equivalent, key selection criteria include its 800MHz full-power bandwidth, dual-channel timing matching, LVDS serialization modes (1-/2-lane), and support for both internal/external reference configurations in a compact 40-pin QFN package.

Technical Context

The LTC2268-12 integrates two independent 12-bit ADC cores with shared PLL-based clock conditioning and a digital serializer driving LVDS output pairs. Its sample-and-hold features 800MHz full-power bandwidth and 0.15ps_RMS jitter, enabling clean undersampling of IF signals up to 140MHz. The device supports differential or single-ended encode inputs and includes a duty-cycle stabilizer for robust clock tolerance.

Digital interface flexibility includes SPI configuration port and parallel mode control via CS/SCK/SDI pins. Output serialization supports 12-/14-/16-bit formats across 1- or 2-lane LVDS, with programmable output current (1.75mA or 3.5mA per lane) and optional on-chip 100Ω termination. Internal reference yields ±1V input range; external reference via SENSE pin enables 1–2V_P–P adjustable range.

Key Specifications

Pinout & Package

40-lead (6mm × 6mm) plastic QFN package with exposed thermal pad (Pin 41 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit, high-speed ADC applications.

Compared with AD9233-125, LTC2268-12 provides essential dual-channel simultaneity and embedded LVDS framing, while LTC2267-12 offers identical functionality at reduced speed and power - making it a validated migration path for cost- or thermal-constrained designs without sacrificing pin or firmware compatibility.

Availability

LTC2268-12 is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio, portable medical imaging, and multichannel test equipment requiring stable component supply and long-term production continuity.

Supply support for LTC2268-12 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving communications, industrial, automotive, and healthcare markets.

The LTC2268-12 belongs to ADI's high-speed precision ADC product line, engineered specifically for demanding communications and instrumentation applications requiring exceptional dynamic range, low jitter, and multichannel coherence.

FAQ

What is the maximum input frequency supported by the LTC2268-12?

The LTC2268-12 features an 800MHz full-power bandwidth, allowing accurate digitization of analog inputs up to that frequency. Performance metrics such as SNR and SFDR are specified up to 140MHz - the highest input frequency tested in the datasheet - with usable undersampling capability extending well beyond, depending on system-level anti-alias filtering and clock jitter constraints. The LTC2268-12 maintains 70.6dB SNR at 140MHz with –1dBFS input.

Does the LTC2268-12 support both internal and external voltage references?

Yes, the LTC2268-12 supports both internal and external reference configurations. Connecting the SENSE pin to VDD selects the internal 1.25V reference and sets the input range to ±1V (2V_P–P). Connecting SENSE to ground disables the internal reference and enables external reference operation, supporting 1–2V_P–P input ranges with user-supplied reference voltage applied to the SENSE pin. The LTC2268-12 datasheet specifies performance for both modes.

How many LVDS data lanes does the LTC2268-12 use, and can this be configured?

The LTC2268-12 supports configurable LVDS serialization: it operates in either 1-lane mode (1 bit per channel per clock edge) or 2-lane mode (2 bits per channel per clock edge), selected via the PAR/SER pin and CS logic. In 2-lane mode, OUT1A+/– and OUT1B+/– carry interleaved bits for Channel 1; similarly for Channel 2. In 1-lane mode, only OUT1A+/– and OUT2A+/– are active. The LTC2268-12 maintains full 125Msps throughput in both configurations.

What is the pipeline latency of the LTC2268-12, and why does it matter?

The LTC2268-12 has a fixed pipeline latency of 6 clock cycles from encode edge to valid LVDS data output. This deterministic latency enables precise timing alignment in FPGA-based digital downconverters and real-time control loops. For example, in a 125MHz system, the latency is exactly 48ns - critical for closed-loop feedback, time-of-flight measurements, and synchronized multi-ADC array processing. The LTC2268-12 guarantees this value across temperature and voltage.

Can the LTC2268-12 operate with a single-ended encode clock?

Yes, the LTC2268-12 supports single-ended encode clock operation: tie ENC– to GND and drive ENC+ with a 0–3.6V logic signal (e.g., 1.8V square wave). Input thresholds are VIH = 1.2V and VIL = 0.6V at VDD = 1.8V. While differential mode delivers optimal jitter performance (0.15ps_RMS), single-ended operation is fully functional and specified - achieving 70.3dB SNR at 70MHz in testing. The LTC2268-12 maintains full specification compliance in either mode.