Analog Devices Inc. DC1532A-I

Overview

LTC2268-12 from Analog Devices (formerly Linear Technology) is a 12-bit, dual-channel, simultaneous-sampling analog-to-digital converter optimized for high-frequency communications signal digitization. It delivers 70.6dB SNR, 88dB SFDR, and ultralow 0.15ps_RMS aperture jitter at 125Msps sampling rate, with full-power bandwidth of 800MHz and single 1.8V supply operation - enabling direct IF sampling in cellular base stations and software-defined radios.

For engineers reviewing the LTC2268-12 datasheet, LTC2268-12 pinout, LTC2268-12 application, or LTC2268-12 equivalent, key selection criteria include its LVDS serial output architecture (1- or 2-lane), differential input range (1–2V_P-P), SPI-configurable operating modes, and guaranteed ±0.3LSB INL over –40°C to +85°C industrial temperature range.

Technical Context

The LTC2268-12 integrates two independent 12-bit ADC cores with shared PLL-based clock conditioning and a digital serializer driving LVDS outputs. Its sample-and-hold front-end supports undersampling up to 800MHz, while internal duty cycle stabilizer ensures full-speed performance across wide encode clock duty cycles (20%–80%).

Dual-channel synchronization is maintained via simultaneous sampling architecture with matched gain/offset (±0.2%FS gain matching, ±3mV offset matching) and low crosstalk (–105dBc). Serial LVDS output supports 12-/14-/16-bit serialization per lane, with programmable output current (1.75mA or 3.5mA) and optional on-chip 100Ω termination.

Key Specifications

Pinout & Package

40-lead (6mm × 6mm) plastic QFN package with exposed thermal pad (Pin 41 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit, high-speed ADC applications.

Compared with AD9233-125, the LTC2268-12 provides true simultaneous dual-channel sampling and LVDS serialization, eliminating inter-channel skew and reducing PCB routing complexity; compared with LTC2267-12, it delivers 20Msps higher throughput at only 54mW additional power - justifying the trade-off in wideband SDR and base station applications.

Availability

LTC2268-12 is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio development, and portable medical imaging systems requiring stable component supply, long-term manufacturability, and industrial temperature grade (–40°C to +85°C) reliability.

Supply support for LTC2268-12 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.

The LTC2268-12 belongs to ADI's high-speed precision ADC product line, engineered specifically for demanding communications and instrumentation applications requiring exceptional dynamic range, low jitter, and multichannel coherence.

FAQ

What is the maximum sampling frequency supported by the LTC2268-12?

The LTC2268-12 supports a maximum sampling frequency of 125Msps, verified across the full industrial temperature range (–40°C to +85°C). This rating assumes proper power supply decoupling, thermal management, and LVDS load compliance. At this rate, the device achieves 70.6dB SNR and 88dB SFDR with a 70MHz input tone - making the LTC2268-12 suitable for wideband IF sampling in LTE and 5G NR infrastructure equipment.

Does the LTC2268-12 support both differential and single-ended analog inputs?

The LTC2268-12 is designed exclusively for differential analog inputs on AIN1+/– and AIN2+/–. It does not support true single-ended analog input operation. However, the encode clock inputs (ENC+/–) accept both differential (LVDS, PECL, sine) and single-ended (TTL, CMOS, 1.8V square wave) drive - with internal termination and biasing configured automatically based on ENC– connection state.

How does the PAR/SER pin affect the functionality of the LTC2268-12?

The PAR/SER pin selects between two distinct configuration interfaces: when tied to GND, the LTC2268-12 enters serial programming mode using SPI (CS/SCK/SDI/SDO); when tied to VDD, it enters parallel programming mode where CS, SCK, SDI, and SDO become direct logic inputs controlling output serialization, current, and termination. This dual-mode flexibility allows the same LTC2268-12 hardware to support either FPGA-based SPI control or simple GPIO-based setup.

What is the purpose of the SENSE pin on the LTC2268-12?

The SENSE pin on the LTC2268-12 configures the reference source and input range: connecting SENSE to VDD selects the internal 1.25V reference and sets the input range to ±1V (2V_P-P); connecting SENSE to GND selects external reference mode and enables 1–2V_P-P programmable input range. The pin accepts voltages from 0.625V to 1.3V, allowing fine-tuned reference scaling for optimal dynamic range utilization.

Can the LTC2268-12 operate with separate analog and digital supplies?

Yes - the LTC2268-12 features independent analog (VDD) and output (OVDD) supply pins, both rated for 1.7V–1.9V operation. This separation isolates sensitive analog circuitry from LVDS output switching noise. While both supplies are typically tied to the same 1.8V rail, best practice is to use separate low-ESR ceramic bypassing (0.1µF per VDD/OVDD pin) and partition ground planes (GND for analog, OGND for outputs) with low-inductance interconnection near the device.