Analog Devices Inc. DC1563A-A

Overview

LTC2315-12 from Analog Devices (formerly Linear Technology) is a 12-bit, 5 Msps successive approximation register (SAR) analog-to-digital converter in an 8-lead TSOT-23 package. It operates from a single 2.7 V to 5.25 V analog supply, integrates a low-drift (20 ppm/°C max) internal reference (2.048 V or 4.096 V), and delivers 72.6 dB SINAD at 500 kHz input frequency - enabling high-fidelity signal digitization in space-constrained, battery-powered data acquisition systems.

For engineers reviewing the LTC2315-12 datasheet, LTC2315-12 pinout, LTC2315-12 application, or LTC2315-12 equivalent, key selection considerations include its 5 Msps throughput with 1-cycle latency, dual-supply flexibility (VDD up to 5.25 V, OVDD from 1.71 V to 5.25 V), nap/sleep power modes (<1 µA sleep current), and guaranteed operation from –40°C to 125°C in H-grade variants.

Technical Context

The LTC2315-12 implements a fully integrated SAR architecture with on-chip bandgap reference, reference buffer, and sample-and-hold. Its timing is governed by an external SPI-compatible serial interface (CS, SCK, SDO), supporting 87.5 MHz maximum SCK frequency and achieving 200 ns minimum throughput time when SCK is held high during acquisition.

It features separate analog (VDD) and digital I/O (OVDD) supplies, enabling interoperability with 1.8 V, 2.5 V, 3.3 V, or 5 V host logic. Power management includes nap mode (1.8 mA, fast wake-up <1 conversion) and sleep mode (0.8 µA typical), with reference recovery time of 1.1 ms after sleep exit due to 2.2 µF REF bypass capacitor recharge.

Key Specifications

Pinout & Package

Package: 8-lead plastic TSOT-23 (0.65 mm pitch), thermally enhanced with exposed pad (not electrically connected). Requires 2.2 µF ceramic bypass capacitors on VDD, REF, and OVDD pins per datasheet layout guidelines.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 12-bit, high-speed SAR ADC applications.

Compared with ADS8860 and MAX11198, the LTC2315-12 uniquely balances 5 Msps speed, integrated dual-range reference, 125°C capability, and best-in-class 72.6 dB SINAD - making it optimal for rugged, high-throughput embedded systems where thermal resilience and analog fidelity are co-prioritized.

Availability

LTC2315-12 is available at Aetrix Electronics and suitable for high-speed data acquisition, handheld terminal interface, and automotive sensor signal conditioning requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for LTC2315-12 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, formed through the acquisition of Linear Technology in 2017.

The LTC2315-12 belongs to ADI's precision SAR ADC product line, designed specifically for compact, low-power, high-speed digitization in instrumentation, medical, and industrial systems where integration, accuracy, and thermal robustness are critical.

FAQ

What is the maximum sampling rate supported by the LTC2315-12?

The LTC2315-12 supports a maximum sampling rate of 5 Msps, achievable only when using the timing pattern where SCK is held high during the acquisition phase (t_ACQ = 40 ns). This yields a minimum throughput time of 200 ns. Other timing configurations (SCK low or continuous) limit throughput to 4.86 Msps due to integer-clocking constraints.

Does the LTC2315-12 require an external reference voltage?

No, the LTC2315-12 does not require an external reference. It integrates a precision bandgap reference and buffer that automatically outputs either 2.048 V (when VDD is 2.7–3.6 V) or 4.096 V (when VDD is 4.75–5.25 V). An external reference may be applied to the REF pin if higher accuracy or custom span is needed, but it is optional.

How does the nap mode of the LTC2315-12 differ from sleep mode in terms of wake-up time and power consumption?

Nap mode draws 1.8 mA and allows wake-up and valid conversion within one SCK cycle, preserving reference stability. Sleep mode draws only 0.8 µA typical but requires 1.1 ms for REF capacitor recharge before accurate conversion - due to full shutdown of the internal bandgap and reference buffer. Use nap for frequent low-latency wake-ups; use sleep for extended idle periods.

Can the LTC2315-12 interface directly with a 1.8 V microcontroller?

Yes, the LTC2315-12 can interface directly with a 1.8 V microcontroller via its dedicated OVDD pin, which accepts 1.71 V to 5.25 V. Setting OVDD = 1.8 V configures SDO output swing and CS/SCK input thresholds to 1.8 V logic levels - eliminating level shifters and simplifying design in mixed-voltage systems.

What is the purpose of the leading zero(s) in the LTC2315-12 serial data output format?

The LTC2315-12 outputs either one or two leading zeros before the 12-bit conversion result (MSB first) to frame the data stream for timing alignment and error detection. One leading zero occurs when SCK is held low during acquisition; two occur when SCK is high or continuous. These zeros provide fixed-width framing (13 or 14 bits total before LSB), easing synchronization in FPGA or MCU firmware.