Analog Devices Inc. DC1564A-A

Overview

DC1564A-A from Analog Devices (formerly Linear Technology) is a dual-channel, 14-bit, 250Msps high-speed analog-to-digital converter designed for RF-sampling and undersampling applications in communications infrastructure. It delivers 70dB SNR, 90dB SFDR, and 1.25GHz full-power bandwidth with DDR LVDS outputs, operating from a single 1.8V supply and supporting pin-compatible 12-bit variants. It is used in cellular basestations and software-defined radios.

For engineers reviewing the DC1564A-A datasheet, DC1564A-A pinout, DC1564A-A application, or DC1564A-A equivalent, key selection criteria include sampling rate scalability (250/210/170Msps variants), low-latency 6-cycle pipeline, integrated clock duty cycle stabilizer, and configurable LVDS output current (1.75mA or 3.5mA).

Technical Context

The DC1564A-A implements a pipelined ADC architecture with simultaneous sampling across two channels, featuring a 1.25GHz sample-and-hold front-end enabling wideband RF input capture without external IF stages. Its digital correction logic compensates for gain, offset, and nonlinearity errors, achieving ±0.85LSB INL and ±0.25LSB DNL over temperature.

It supports flexible clocking via differential ENC+/ENC– inputs compatible with sine wave, PECL, LVDS, TTL, or CMOS sources, and includes an optional duty cycle stabilizer to maintain performance across non-50% clock duty cycles. The SPI interface enables runtime configuration of sleep/nap modes, output current, and clock phase alignment.

Key Specifications

Pinout & Package

DC1564A-A is housed in a 64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND). The package requires soldering the exposed pad to PCB ground for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed dual-channel ADC applications.

Compared with DC1564A-A, AD9680BCPZ-500 offers double the sampling rate and modern serial interface but doubles power and lacks pin compatibility; LTC2268IUP-14 provides identical resolution and package at half the speed and power, making it a footprint-compatible downgrade for less demanding RF sampling tasks.

Availability

DC1564A-A is available at Aetrix Electronics and suitable for cellular basestations, software-defined radios, and medical imaging systems requiring stable component supply and long-term industrial availability.

Supply support for DC1564A-A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and RF ICs for precision and high-speed applications.

The DC1564A-A belongs to the LTC215x family of ultra-high-speed dual ADCs engineered specifically for RF-sampling architectures in wireless infrastructure and instrumentation, emphasizing AC performance, low latency, and flexible digital interface options.

FAQ

What is the maximum input frequency supported by DC1564A-A?

The DC1564A-A features a 1.25GHz full-power bandwidth, enabling reliable undersampling of input signals up to this frequency while maintaining specified SNR and SFDR performance. At 907MHz input and 250Msps sampling, typical SFDR remains ≥85dBFS, confirming usability well into L-band.

Does DC1564A-A support both internal and external voltage references?

Yes, DC1564A-A supports both reference modes: connecting SENSE to VDD selects the internal 1.25V reference and ±0.75V input range; applying 1.20V–1.30V to SENSE selects external reference mode with ±0.6×VSENSE input range. VREF pin outputs the internal reference and must be bypassed with 2.2µF.

How does the DDR LVDS interface of DC1564A-A reduce FPGA pin count?

DC1564A-A uses double-data-rate LVDS outputs: each differential pair carries two bits per clock edge (even bits on CLKOUT+ low, odd bits on high), reducing the total number of data lines required by half. For 14-bit dual channels, only 14 LVDS pairs (28 pins) are needed instead of 28 single-data-rate lines.

Can DC1564A-A operate with non-50% duty cycle clocks?

Yes, DC1564A-A includes an optional clock duty cycle stabilizer enabled via SPI register. When active, it corrects input clock asymmetry and maintains full 70dB SNR and 90dB SFDR performance across 30%–70% duty cycles, eliminating need for external clock conditioning circuits.

What is the purpose of the PAR/SER pin on DC1564A-A?

The PAR/SER pin (Pin 63) selects programming mode: tied to GND enables full-featured serial SPI interface (CS/SCK/SDI/SDO); tied to VDD enables simplified parallel mode where SDI and SCK become direct logic controls for LVDS current and sleep mode. It must be hardwired-not driven dynamically.