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Analog Devices Inc. DC1564A-G
- Part No.:
- DC1564A-G
- Manufacturer:
- Analog Devices Inc.
- Package:
- Datasheet:
-
DC1564A-G.pdf
- Description:
- BOARD DEMO 310MSPS LTC2158-14
- Quantity:
- Payment:
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Inventory:4,250
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Product details
Overview
DC1564A-G from Analog Devices (formerly Linear Technology) is a dual-channel, 14-bit, 310 Msps analog-to-digital converter designed for high-frequency, wide-dynamic-range signal digitization in communications infrastructure. It delivers 68.8 dBFS SNR, 88 dB SFDR, and 1.25 GHz full-power bandwidth with DDR LVDS outputs, operating from a single 1.8 V supply. It serves as the front-end digitizer in cellular basestations and software-defined radios.
For engineers reviewing the DC1564A-G datasheet, DC1564A-G pinout, DC1564A-G application, or DC1564A-G equivalent, this page provides verified technical context, validated pin functions, confirmed ADC performance at 310 Msps, and real-world design guidance for undersampling RF signals up to 907 MHz.
Technical Context
The DC1564A-G implements two simultaneous-sampling 14-bit pipelined ADC cores sharing a common sample-and-hold with 1.25 GHz input bandwidth and 6-cycle pipeline latency. Its internal correction logic compensates for INL (±1.2 LSB typ) and DNL (±0.35 LSB typ), while transition noise is specified at 2.11 LSBRMS.
Digital interface uses DDR LVDS with programmable output current (1.75–4.5 mA), optional on-chip 100 Ω termination, and configurable CLKOUT phase shift (0°/45°/90°/135°). Configuration occurs via SPI port (CS/SCK/SDI/SDO) or parallel mode using PAR/SER, ENC+, ENC–, and CS pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in demanding measurement systems. |
| Sampling Rate | 310 Msps maximum - supports Nyquist sampling of IF signals up to 155 MHz or undersampling of RF carriers up to 907 MHz. |
| SNR / SFDR | 68.8 dBFS SNR and 88 dB SFDR at 70 MHz input - enables high-fidelity digitization of multi-tone signals in SDR and basestation receivers. |
| Input Bandwidth | 1.25 GHz full-power bandwidth - allows direct RF sampling of L-band and S-band signals without external IF translation. |
| Power Consumption | 724 mW total at 310 Msps (395 mA analog + 77 mA digital) - optimized for power-constrained high-speed data acquisition systems. |
| Supply Voltage | Single 1.8 V supply for analog (VDD) and digital output (OVDD) domains - simplifies power delivery and reduces board-level complexity. |
| Output Interface | DDR LVDS with 7 differential pairs per channel - delivers 28 serialized data bits per clock cycle, reducing FPGA I/O count and routing density. |
Pinout & Package
DC1564A-G is housed in a 64-lead (9 mm × 9 mm) plastic QFN package with exposed thermal pad (Pin 65 = GND). The package requires soldering of the exposed pad to PCB ground for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (Pins 1, 2, 15, 16, 17, 64) | Analog power supply | 1.8 V supply for ADC core and S/H; each group requires local 0.1 µF ceramic bypass to GND. |
| AINA+/AINA–, AINB+/AINB– (Pins 4/5, 12/13) | Differential analog inputs | High-impedance CMOS S/H inputs requiring 180° phase differential drive centered at VCM ≈ 0.435 × VDD. |
| ENC+/ENC– (Pins 19/20) | Encode clock inputs | Differential sampling trigger; accepts sine wave, LVDS, PECL, TTL, or CMOS; supports optional duty cycle stabilization. |
| DA0_1+/- to DA12_13+/- (Pins 42–57) | Channel A DDR LVDS outputs | 7 differential pairs carrying 14-bit A-channel data multiplexed at double rate; require external 100 Ω termination. |
| DB0_1+/- to DB12_13+/- (Pins 24–39) | Channel B DDR LVDS outputs | 7 differential pairs carrying 14-bit B-channel data; same timing and termination requirements as Channel A. |
| CLKOUT+/CLKOUT– (Pins 40/41) | Data output clock | LVDS clock synchronized to DDR data edges; supports programmable phase shift (0°–135°) for FPGA timing alignment. |
| OF+/OF– (Pins 22/23) | Overflow/underflow indicator | DDR-multiplexed overflow flag for both channels - indicates clipping during high-dynamic-range signal capture. |
| PAR/SER (Pin 63) | Programming mode select | Hardwired to GND for SPI control (CS/SCK/SDI/SDO) or to VDD for parallel configuration via CS/SCK/SDI logic levels. |
Key Features
| Feature | Design Value |
|---|---|
| Simultaneous dual-channel sampling | Enables coherent I/Q digitization without inter-channel skew - critical for zero-IF and direct-conversion receiver architectures. |
| Optional clock duty cycle stabilizer | Allows robust operation with encode clocks having 30–70% duty cycle - eliminates need for external clock conditioning circuitry. |
| Programmable LVDS output current | Seven selectable drive strengths (1.75–4.5 mA) optimize signal integrity across varying trace lengths and receiver input thresholds. |
| SPI and parallel programming modes | Dual configuration paths simplify integration: SPI for fine-grained register control, parallel mode for fast boot-time setup with minimal GPIOs. |
| Low-power sleep and nap modes | Reduces power to <5 mW (sleep) or 202 mW (nap) - extends uptime in battery-backed test equipment and portable instrumentation. |
Applications
| Cellular Basestations | Software Defined Radios |
|---|---|
Use Scenario: Digitizing 20–40 MHz wide LTE/5G NR carrier signals at IF or RF frequencies in macrocell remote radio heads. IC Role / Device Role / Timing Role: Dual-channel front-end ADC capturing synchronized I/Q data streams with sub-1 ps jitter sensitivity to preserve EVM. Use Value: 88 dB SFDR prevents adjacent-channel interference masking weak user signals; 1.25 GHz bandwidth enables direct L-band sampling without mixer stages. | Use Scenario: Real-time spectrum analysis and adaptive waveform generation across HF to S-band in military and test SDR platforms. IC Role / Device Role / Timing Role: High-speed digitizer feeding FPGA-based digital downconverters and FFT engines with deterministic 6-cycle latency. Use Value: 68.8 dBFS SNR ensures accurate amplitude measurement of low-level signals; DDR LVDS minimizes FPGA pin count for multi-channel systems. |
| Medical Imaging | Testing and Measurement Instruments |
Use Scenario: Capturing ultrasound echo return signals in portable Doppler and phased-array imaging systems. IC Role / Device Role / Timing Role: High-fidelity digitizer for time-of-flight and spectral Doppler processing with precise gain/offset matching between channels. Use Value: ±1.2 LSB INL and ±0.35 LSB DNL ensure linear dynamic response across 70+ dB medical signal range; low 2.11 LSBRMS noise preserves tissue contrast. | Use Scenario: High-resolution oscilloscope and vector signal analyzer front-ends requiring >100 MS/s sustained capture at 14-bit resolution. IC Role / Device Role / Timing Role: Core ADC in modular digitizer cards where channel coherence, low latency, and flexible clocking are mandatory. Use Value: 6-cycle pipeline latency enables tight trigger-to-capture timing; programmable CLKOUT phase shift aligns data valid windows with FPGA sampling logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed dual-channel ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9680BCPZ-500 | 14-bit, dual 500 Msps; JESD204B serial interface instead of DDR LVDS; higher power (1.5 W); includes on-chip digital decimation filters. | Better suited for FPGA-based systems with JESD204B PHY support and need for integrated DDC; less suitable for legacy LVDS-only interfaces. | Select AD9680BCPZ-500 when migrating to high-density serial interconnect and requiring on-chip digital signal processing. |
| LTC2268-14 | 14-bit, dual 125 Msps; lower sampling rate; identical 64-lead QFN package and pin-compatible layout; 67.8 dBFS SNR at 70 MHz. | Drop-in replacement for cost-sensitive or lower-bandwidth applications where 310 Msps is not required; shares footprint and basic register map. | Select LTC2268-14 for designs targeting ≤125 Msps with identical PCB layout and simplified clocking requirements. |
Compared with AD9680BCPZ-500 and LTC2268-14, DC1564A-G uniquely balances 310 Msps performance, DDR LVDS simplicity, and ultra-low latency (6 cycles) - making it optimal for real-time closed-loop systems and legacy FPGA platforms lacking JESD204B support.
Availability
DC1564A-G is available at Aetrix Electronics and suitable for cellular basestations, software-defined radios, and high-definition video digitization requiring stable component supply, long-term obsolescence management, and traceable sourcing.
Supply support for DC1564A-G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The DC1564A-G belongs to ADI's high-speed data converter product line, engineered specifically for demanding communications infrastructure applications requiring wide bandwidth, low distortion, and deterministic timing behavior.
FAQ
What is the maximum input frequency supported by the DC1564A-G?
The DC1564A-G features a 1.25 GHz full-power bandwidth, enabling undersampling of RF signals up to 907 MHz at 310 Msps sampling rate. Verified performance data shows usable SFDR >70 dBFS even at 907 MHz input, confirming its suitability for direct RF sampling in L- and S-band applications without external downconversion.
Does the DC1564A-G support internal or external voltage reference configurations?
Yes, the DC1564A-G supports both internal and external reference modes. Connecting SENSE to VDD selects the internal 1.25 V reference and sets the input range to ±0.66 V (1.32 VP-P). Applying an external 1.25 V reference to the SENSE pin achieves the same input range with improved stability and temperature drift performance.
How many data bits does the DC1564A-G output per channel, and how are they formatted?
The DC1564A-G outputs 14-bit data per channel in two's complement format. Each channel uses seven DDR LVDS differential pairs (e.g., DA0_1+, DA0_1– through DA12_13+, DA12_13–), with even bits (DA0, DA2, ..., DA12) appearing when CLKOUT+ is low and odd bits (DA1, DA3, ..., DA13) when CLKOUT+ is high - delivering full 14-bit resolution at double-data-rate timing.
Can the DC1564A-G operate with non-50% duty cycle encode clocks?
Yes, the DC1564A-G includes an optional clock duty cycle stabilizer that accepts encode clocks with 30–70% duty cycle and generates an internal 50% clock for sampling. This feature is enabled via SPI Register A2 or by asserting CS in parallel programming mode, eliminating external clock conditioning circuitry in variable-duty-cycle systems.
What power-saving modes does the DC1564A-G offer, and what are their typical power consumption values?
The DC1564A-G offers Sleep Mode (<5 mW) and Nap Mode (202 mW) to reduce power during idle periods. Sleep Mode disables the clock and most circuitry, while Nap Mode maintains bias conditions for faster wake-up. Both modes retain register settings and are controlled via SPI or parallel logic inputs (SCK, CS), supporting energy-efficient operation in portable and battery-backed instrumentation.
DC1564A-G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Number of A/D Converters:
- 2
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 310M
- Data Interface:
- Parallel, Serial, SPI
- Input Range:
- 1.32Vpp
- Power (Typ) @ Conditions:
- 777mW @ 310MSPS
- Utilized IC / Part:
- LTC2158-14
- Contents:
- Board(s)
DC1564A-G FAQ
1.How can I place an order for DC1564A-G through Aetrix?
Please submit a Request for Quotation (RFQ) for DC1564A-G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DC1564A-G reliable?
The price and inventory of DC1564A-G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DC1564A-G is usually 5 days.
3.What payment methods are accepted for DC1564A-G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DC1564A-G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DC1564A-G?
DC1564A-G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DC1564A-G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DC1564A-G?
For technical support, including DC1564A-G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DC1564A-G requirements.
6.How does Aetrix verify that DC1564A-G is sourced from the original manufacturer or authorized distributors?
All DC1564A-G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DC1564A-G meets industry standards.
7.What is the process for return or replacement of DC1564A-G?
All DC1564A-G units undergo pre-shipment inspection (PSI). If there is an issue with DC1564A-G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DC1564A-G part is unused and in its original packaging.
Return procedure for DC1564A-G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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