Analog Devices Inc. DC1620A-D

Overview

DC1620A-D from Analog Devices (formerly Linear Technology) is a dual-channel, 16-bit, 65Msps simultaneous-sampling analog-to-digital converter designed for high-dynamic-range signal digitization in RF and IF receiver chains. It delivers 77dB SNR, 90dB SFDR, and ultralow 0.07psRMS jitter, enabling undersampling of 70MHz+ IF signals in cellular base stations and software-defined radios.

For engineers reviewing the DC1620A-D datasheet, DC1620A-D pinout, DC1620A-D application, or DC1620A-D equivalent, key selection criteria include its dual-channel simultaneity, 550MHz full-power bandwidth, selectable CMOS/DDR-CMOS/DDR-LVDS outputs, 1.8V single-supply operation, and support for differential or single-ended clock inputs with duty cycle stabilization.

Technical Context

The DC1620A-D implements two independent 16-bit SAR-based ADC cores with shared sample-and-hold circuitry optimized for wideband, low-jitter acquisition. Its architecture supports true simultaneous sampling across both channels, critical for I/Q demodulation and phase-coherent multi-antenna systems.

It integrates configurable digital output drivers (CMOS, DDR-CMOS, or DDR-LVDS), a serial SPI interface for register configuration, and power management modes (Nap at 10mW, Sleep at 1mW). Input range is selectable between 1VP-P and 2VP-P, with internal or external reference options and 0.5•VDD common-mode bias outputs (VCM1/VCM2).

Key Specifications

Pinout & Package

DC1620A-D is housed in a 64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND, must be soldered). The package supports high-density PCB layouts and efficient thermal dissipation (θJA = 28°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 16-bit, high-speed ADC applications.

Compared with AD9653BCPZ-125 and ADS52J90IRGCT, DC1620A-D uniquely balances 65Msps dual-channel performance, 77dB SNR, sub-0.1ps jitter, and ultra-low 160mW power-making it optimal for thermally constrained, phase-coherent, and battery-aware RF/data acquisition systems.

Availability

DC1620A-D is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio development, and portable medical imaging requiring stable component supply and long-term production continuity.

Supply support for DC1620A-D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving communications, industrial, automotive, and healthcare markets.

The DC1620A-D belongs to ADI's high-speed precision ADC product line, engineered specifically for wideband, low-jitter digitization in RF receiver front-ends and instrumentation systems demanding simultaneous dual-channel fidelity.

FAQ

What is the maximum analog input frequency supported by the DC1620A-D?

The DC1620A-D features a 550MHz full-power bandwidth, allowing it to accurately digitize analog signals up to that frequency without significant amplitude roll-off. This enables direct undersampling of UHF and L-band RF signals-for example, cleanly capturing 70MHz or 140MHz IF inputs while maintaining 77dB SNR and 90dB SFDR. The specification is verified per Figure 6 test circuit in the official datasheet and applies across all operating temperatures.

Does the DC1620A-D support single-ended clock input?

Yes, the DC1620A-D supports single-ended encode operation: tie ENC– to GND and drive ENC+ with a 1.8V square wave or sine wave. In this mode, VIH is 1.2V and VIL is 0.6V (VDD = 1.8V), with input resistance of 30kΩ and capacitance of 3.5pF. Differential mode remains preferred for lowest jitter (0.07psRMS vs 0.09psRMS), but single-ended operation is fully characterized and supported in all speed grades (65/40/25Msps).

What output interface options does the DC1620A-D provide?

The DC1620A-D offers three configurable digital output modes: full-rate CMOS, double-data-rate CMOS (DDR-CMOS), and double-data-rate LVDS (DDR-LVDS). Output voltage swing is set by OVDD (1.2V–1.8V for CMOS, fixed 1.8V for LVDS). DDR-LVDS uses on-chip 100Ω termination and delivers 247–454mV differential swing; CMOS modes support programmable drive strength and are compatible with standard FPGA I/O banks.

How does the PAR/SER pin affect configuration of the DC1620A-D?

The PAR/SER pin selects between two mutually exclusive programming interfaces: when grounded, it enables full-featured SPI control (CS/SCK/SDI/SDO) for configuring all operating modes including output format, randomizer, and duty cycle stabilizer; when tied to VDD, it enables parallel logic control where CS and SCK become dedicated function pins (e.g., CS toggles duty cycle stabilizer, SCK selects output mode). PAR/SER must be hardwired-not driven by logic-to ensure reliable startup and configuration.

What power-saving modes are available on the DC1620A-D, and how quickly can it resume sampling?

The DC1620A-D provides two low-power states: Nap mode (10mW) and Sleep mode (1mW). In Nap mode, the analog core remains biased and resumes full-speed sampling within 100ns of wake-up signal assertion. Sleep mode powers down most circuitry and requires ~1µs to re-stabilize references and clocks before valid conversion. Both modes are controlled via SPI register writes or parallel logic inputs, and are fully characterized across temperature for use in portable and energy-conscious systems.