Analog Devices Inc. DC1620A-O

Overview

DC1620A-O from Analog Devices (formerly Linear Technology) is a high-performance evaluation board for the LTC2145-12, a 12-bit, 125Msps dual-channel simultaneous-sampling ADC. It supports CMOS, DDR CMOS, and DDR LVDS output modes, delivers 70.6dB SNR and 89dB SFDR, operates from a single 1.8V supply, and targets RF sampling in cellular base stations and software-defined radios.

For engineers reviewing the DC1620A-O datasheet, DC1620A-O pinout, DC1620A-O application, or DC1620A-O equivalent, this page provides verified board-level specifications, supported ADC variants (LTC2145-12/LTC2144-12/LTC2143-12), power sequencing guidance, analog input interface details, and FPGA-compatible digital output timing - all critical for rapid prototyping of wideband data acquisition systems.

Technical Context

The DC1620A-O implements full signal chain support for the LTC2145-12 family, including precision 750MHz S/H front-end, selectable 1VP-P to 2VP-P differential input range, on-board clock conditioning with duty cycle stabilizer, and configurable output drivers for CMOS (1.2–1.8V OVDD) or DDR LVDS (1.75mA/3.5mA modes). It routes all 64 QFN pins to accessible test points and headers.

Board-level design includes independent analog (VDD/GND) and digital (OVDD/OGND) power domains, low-noise LDOs, calibrated reference buffers (REFH/REFL), and SPI-controlled configuration via onboard ADSP-BF533 DSP or external host. The layout adheres to RF-sensitive mixed-signal practices: ground plane integrity, controlled-impedance traces, and exposed pad soldering per LTC2145 QFN thermal requirements.

Key Specifications

Availability

DC1620A-O is available at Aetrix Electronics and suitable for cellular infrastructure, medical ultrasound imaging, and portable spectrum analyzers requiring stable component supply and validated reference designs for high-speed dual ADC integration.

Supply support for DC1620A-O includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving communications, industrial, automotive, and healthcare markets.

The DC1620A-O belongs to ADI's Linear Technology evaluation board portfolio, designed specifically to accelerate development of high-fidelity, wideband data acquisition systems using ultra-low-jitter, dual-channel ADCs like the LTC2145 family.

FAQ

What is the primary function of the DC1620A-O evaluation board?

The DC1620A-O evaluation board is a fully assembled and tested platform for evaluating the LTC2145-12, LTC2144-12, and LTC2143-12 dual-channel 12-bit ADCs. It provides all necessary power regulation, clock conditioning, analog input interface, and configurable digital output routing to validate performance metrics such as SNR, SFDR, and crosstalk in real-world signal chains. DC1620A-O enables rapid characterization without custom PCB design.

Which ADC variants are supported by the DC1620A-O board?

The DC1620A-O board supports three speed grades of the same 64-pin QFN package: LTC2145-12 (125Msps), LTC2144-12 (105Msps), and LTC2143-12 (80Msps). All share identical pinout, power architecture, and feature set - only sample rate and corresponding power consumption differ. DC1620A-O accommodates all via jumper-selectable clock and power configurations.

Does the DC1620A-O support DDR LVDS output mode, and what are the key implementation details?

Yes, DC1620A-O fully supports DDR LVDS output mode for the LTC2145-12 family. It provides on-board 100Ω differential termination, selectable 1.75mA or 3.5mA output current modes, and matched-length differential trace routing to SMA connectors. The OVDD rail is configured for 1.8V, and common-mode voltage is stabilized at 1.25V. DC1620A-O's layout ensures <0.3ns inter-pair skew - critical for timing alignment in FPGA-based capture systems.

How is analog input common-mode bias handled on the DC1620A-O board?

The DC1620A-O routes VCM1 and VCM2 - the internal 0.5×VDD common-mode bias outputs from the LTC2145-12 - directly to the analog input SMA connectors. Each channel's differential input pair (AIN1+/AIN1–, AIN2+/AIN2–) is AC-coupled and terminated to 50Ω, with VCM bias applied through 0.1μF ceramic capacitors. This eliminates external bias networks and maintains optimal 750MHz full-power bandwidth per the datasheet specification for DC1620A-O.

Can the DC1620A-O be used with an external clock source, and what clock conditioning features does it include?

Yes, DC1620A-O accepts external single-ended or differential clock signals via SMA connector and includes on-board clock conditioning circuitry: a duty cycle stabilizer (enabled via CS pin), optional clock buffer, and low-jitter (<0.1ps RMS) distribution network. The board supports ENC+/ENC– differential drive with 0.2–3.6V input range and provides CLKOUT+/- outputs for feedback or daisy-chaining. These features ensure robust timing integrity for undersampling applications up to 140MHz input - a core capability of DC1620A-O.