Analog Devices Inc. DC1805A-E

Overview

DC1805A-E from Analog Devices is a demonstration board for the LTC6655LN-2.5 precision voltage reference IC, delivering 2.5V output with 0.21ppm RMS (10Hz–1kHz) noise, 2ppm/°C max drift, ±0.025% initial accuracy, and operation from –40°C to 125°C - used in high-resolution data acquisition and instrumentation calibration circuits.

For engineers reviewing the DC1805A-E datasheet, DC1805A-E pinout, DC1805A-E application, or DC1805A-E equivalent, this page provides verified functional context, validated noise-reduction implementation details, LS8 package thermal stability metrics, shutdown current validation (<20µA), and confirmed compatibility with LTC6655LN-2.5 in hermetic 5mm × 5mm ceramic LCC packaging.

Technical Context

The DC1805A-E implements the LTC6655LN-2.5 in its high-stability LS8 package, featuring a dedicated NR (Noise Reduction) pin that accepts a 100µF capacitor to reduce wideband noise by >50% versus standard LTC6655 variants. It supports dual-output configuration via VOUT_F and NR pins, with star-grounded GND connections at Pin 4 per layout guidelines.

Designed for metrology-grade applications, the board validates the LTC6655LN-2.5's low dropout (500mV), ±5mA source/sink capability, and load regulation <14ppm/mA (LTC6655LNMS8) or <70ppm/mA (LTC6655LNLS8), while maintaining thermal hysteresis of 30ppm (–40°C to 85°C) and long-term drift of 20ppm/√kHr in the LS8 variant.

Key Specifications

Availability

DC1805A-E is available at Aetrix Electronics and suitable for high-precision instrumentation, automated test equipment, and medical diagnostics requiring stable component supply, traceable sourcing, and long-lifecycle support.

Supply support for DC1805A-E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision measurement and control.

The DC1805A-E belongs to Analog Devices' precision reference evaluation platform family, designed to validate LTC6655LN series performance in real-world PCB layouts, emphasizing noise reduction, thermal stability, and hermetic packaging advantages for metrology applications.

FAQ

What is the primary function of the DC1805A-E evaluation board?

The DC1805A-E evaluation board demonstrates the LTC6655LN-2.5 precision voltage reference IC in its LS8 hermetic ceramic package. It validates key specifications including 0.12ppm_P-P low-frequency noise (with 100µF NR capacitor), 2ppm/°C temperature coefficient, ±0.025% initial accuracy, and thermal hysteresis of 30ppm over –40°C to 85°C - all measured under controlled conditions per Analog Devices' Rev. J datasheet. The DC1805A-E enables rapid prototyping of high-stability reference circuits for instrumentation-grade designs.

Does the DC1805A-E support both MSOP and LS8 package variants of the LTC6655LN-2.5?

No, the DC1805A-E is specifically configured for the LTC6655LN-2.5 in the 8-pin LS8 (5mm × 5mm ceramic LCC) package, not the MSOP variant. Its layout implements star grounding at Pin 4, accommodates the NR pin with recommended 100µF decoupling, and leverages the LS8's hermetic construction to achieve 30ppm thermal hysteresis and no humidity sensitivity - features not replicated in the plastic MSOP version. The DC1805A-E does not support physical or electrical substitution with MSOP-based LTC6655LN-2.5 variants.

How is noise reduction implemented on the DC1805A-E using the NR pin?

Noise reduction on the DC1805A-E is implemented by connecting a 100µF capacitor between the NR pin (Pin 6) and ground, as specified in the LTC6655LN-2.5 datasheet Rev. J. This configuration reduces 0.1Hz–10Hz peak-to-peak noise from 0.25ppm to 0.12ppm and 10Hz–1kHz RMS noise from 0.67ppm to 0.21ppm. The DC1805A-E board includes footprint and routing optimized for low-ESR electrolytic or tantalum capacitors, ensuring stable bandwidth control and avoiding peaking above 100kHz - directly validating the noise-bandwidth trade-off documented in Figure 34 and Figure 35 of the LTC6655/LTC6655LN datasheet.

What are the validated thermal performance metrics for the DC1805A-E with LTC6655LN-2.5?

The DC1805A-E validates the LTC6655LN-2.5's thermal performance in the LS8 package across –40°C to 125°C: thermal hysteresis is confirmed at 30ppm (–40°C to 85°C), long-term drift at 20ppm/√kHr, and temperature coefficient ≤2ppm/°C. These values are measured per Analog Devices' characterization methodology and reflect the LS8's hermetic sealing and low-stress die attach - distinct from MSOP variants, which exhibit higher hysteresis (60ppm) and drift (60ppm/√kHr). The DC1805A-E layout minimizes thermal gradients via symmetric copper pours and isolated ground planes to preserve these metrics in application circuits.

Can the DC1805A-E be used to evaluate load regulation and line regulation of the LTC6655LN-2.5?

Yes, the DC1805A-E supports full validation of load and line regulation per the LTC6655LN-2.5 datasheet Rev. J. It enables measurement of load regulation <70ppm/mA (sinking) and <14ppm/mA (sourcing) under ±5mA loads, and line regulation ≤25ppm/V over VIN = 3.0V to 13.2V. Test points for VIN, VOUT_F, SHDN, and NR allow direct oscilloscope or DMM probing during dynamic load steps (e.g., 5mA sourcing/sinking transients shown in Figures F05–F07), confirming the reference's ability to maintain <0.1% output error across operating conditions - critical for high-resolution ADC biasing in data acquisition systems.