Analog Devices Inc. DC1974A-C

Overview

LTC2122 from Analog Devices (formerly Linear Technology) is a dual-channel, 14-bit, 170Msps analog-to-digital converter with JESD204B serial interface. It performs simultaneous sampling of high-frequency wide-dynamic-range signals, delivering 70dBFS SNR and 90dBFS SFDR at 70MHz input, and supports undersampling up to 1.25GHz full-power bandwidth. It is used in cellular base station receivers requiring deterministic latency and multi-ADC synchronization.

For engineers reviewing the LTC2122 datasheet, LTC2122 pinout, LTC2122 application, or LTC2122 equivalent, key selection considerations include JESD204B subclass 1/2 support, dual-lane vs. single-lane 6.0Gbps operation, 1.8V analog supply with 751mW total power, CML output drive capability, and SPI-configurable clock divider/duty cycle stabilizer.

Technical Context

The LTC2122 integrates two independent 14-bit ADC cores sharing a common DEVCLK input, with optional divide-by-two circuitry and duty cycle stabilizer enabling robust sampling across wide clock duty cycles. Its JESD204B serializer supports both subclass 1 (SYSREF-triggered initialization) and subclass 2 (SYNC~-triggered initialization), ensuring deterministic latency for time-aligned multi-device systems.

Each channel features dedicated CML output pairs (CMLOUT_A0±, CMLOUT_B0±) configurable for either two-lane (3.4Gbps per lane) or one-lane (6.0Gbps shared) operation. The internal reference generates 1.25V VREF and 0.435×VDD VCM, while SENSE pin selection enables ±0.75V (internal) or ±0.6×VSENSE (external) input ranges with 1.5VP-P differential compliance.

Key Specifications

Pinout & Package

48-lead (7mm × 7mm) plastic QFN package with exposed thermal pad (Pin 49 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed dual-channel ADC applications.

Compared with AD9680BCPZ-500 and ADS54J60IRGC, the LTC2122 offers optimal balance of 170Msps performance, 751mW power efficiency, and flexible subclass 1/2 support - making it ideal for cost- and thermally constrained communications infrastructure where full 500Msps capability is unnecessary.

Availability

LTC2122 is available at Aetrix Electronics and suitable for cellular base stations, software-defined radios, medical ultrasound systems, and test & measurement instrumentation requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for LTC2122 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.

The LTC2122 belongs to ADI's high-speed data converter product line, designed specifically for demanding wireless infrastructure and instrumentation applications requiring high dynamic range, low power, and JESD204B interoperability.

FAQ

What is the maximum input frequency supported by the LTC2122?

The LTC2122 has a 1.25GHz full-power bandwidth, enabling direct RF sampling of signals up to that frequency. At 170Msps sampling rate, it supports undersampling of L-band (1–2GHz) and S-band (2–4GHz) signals, provided input anti-alias filtering and layout maintain signal integrity into the ADC's analog input pins.

Does the LTC2122 support both JESD204B subclass 1 and subclass 2?

Yes, the LTC2122 supports both JESD204B subclass 1 and subclass 2. Subclass 1 uses SYSREF+ and SYSREF– for deterministic latency initialization, while subclass 2 uses SYNC~+ and SYNC~– for the same purpose. The device automatically detects and responds to the appropriate signal based on configuration and timing context.

What is the role of the SENSE pin on the LTC2122?

The SENSE pin on the LTC2122 selects the reference mode: connecting SENSE to VDD enables the internal 1.25V reference and ±0.75V input range; applying 1.2–1.3V externally sets an input range of ±0.6 × VSENSE. This allows system-level optimization of dynamic range and gain matching across multiple LTC2122 devices.

Can the LTC2122 operate with a single JESD204B lane for both channels?

Yes, the LTC2122 supports single-lane operation at up to 6.0Gbps for both ADC channels combined, reducing PCB layer count and FPGA pin utilization. In this mode, CMLOUT_A0± carries interleaved data from both channels, while CMLOUT_B0± remains inactive - verified in the functional block diagram and timing specifications.

What power-saving modes does the LTC2122 provide?

The LTC2122 provides two low-power states: Nap mode draws 433mW and retains register settings and clock domain alignment; Sleep mode draws only 2mW but requires reinitialization of the JESD204B link and SPI registers upon wake-up. Both modes are controlled via SPI register writes and support rapid transition for TDD-based systems.