Analog Devices Inc. DC2222A-C
- Part No.:
- DC2222A-C
- Manufacturer:
- Analog Devices Inc.
- Package:
- Datasheet:
-
DC2222A-C.pdf
- Description:
- DEMO BOARD FOR LTC2512-24
- Quantity:
- Payment:

- Shipping:

Inventory:3,617
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2512-24 from Analog Devices (formerly Linear Technology) is a 24-bit successive approximation register (SAR) analog-to-digital converter with integrated configurable digital filter, operating from a single 2.5V supply and supporting ±VREF differential input range up to 5.1V reference. It delivers dual simultaneous outputs: a 24-bit low-noise filtered code (117dB DR at 50ksps) and a 22-bit no-latency composite code (14-bit differential + 8-bit common-mode), in a 24-lead 7mm × 4mm DFN package. It is used in high-accuracy seismic data acquisition systems requiring ultra-low INL (±1ppm typ) and relaxed anti-aliasing.
For engineers reviewing the LTC2512-24 datasheet, LTC2512-24 pinout, LTC2512-24 application, or LTC2512-24 equivalent, key selection considerations include its dual-output architecture, pin-strappable down-sampling factor (4–32), guaranteed 24-bit no-missing-codes performance, SPI-compatible 1.8V–5V I/O, and synchronization capability across multiple devices via SYNC pin.
Technical Context
The LTC2512-24 implements a charge redistribution SAR core followed by a configurable flat-passband digital lowpass filter that performs decimation and noise shaping. Its dual-output path separates high-precision filtered data (SDOA) from real-time composite data (SDOB), enabling concurrent high-resolution measurement and fast control-loop feedback.
Filter configuration is set by SEL0/SEL1 pins, selecting down-sampling factors of 4, 8, 16, or 32 - directly determining output data rate (400ksps to 50ksps) and dynamic range (108dB to 117dB). Synchronization across multiple devices is achieved via the dedicated SYNC input, aligning digital filter phases without external timing coordination.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution (Filtered) | 24-bit with guaranteed no missing codes - ensures monotonicity and full-scale linearity for metrology-grade measurements. |
| Dynamic Range | 117dB typical at 50ksps (DF=32) - enables detection of microvolt-level signals in high-noise industrial environments. |
| INL Error | ±1ppm typical - corresponds to <0.00002% FSR error, critical for calibration-grade instrumentation. |
| Output Data Rates | SDOA: up to 400ksps; SDOB: up to 1.6Msps - supports both precision logging and real-time monitoring on same device. |
| Reference Range | 2.5V to 5.1V - allows optimization of LSB size (596nV at 5V ref) and SNR across varying signal amplitudes. |
| Power Consumption | 30mW at 1.6Msps - achieves high resolution with low thermal load in space-constrained ATE and portable test equipment. |
| Common-Mode Range | 0V to VREF - simplifies front-end design by accepting arbitrary unipolar/bipolar/pseudo-differential inputs without level-shifting. |
Pinout & Package
Package: 24-lead plastic DFN (7mm × 4mm), exposed pad (Pin 25) connected to GND and required to be soldered to PCB ground plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RDLA (1) | Filtered Output Enable | Active-low control for SDOA; enables 24-bit filtered serial output when asserted. |
| RDLB (2) | No-Latency Output Enable | Active-low control for SDOB; enables 22-bit composite output (14+8) with zero-cycle latency. |
| VDD (3) | Analog Core Supply | 2.5V ±62.5mV supply for SAR core and internal references; requires 10µF ceramic bypass. |
| IN+ / IN– (5,6) | Differential Analog Inputs | Accept ±VREF differential swing with 0V–VREF common-mode range; input capacitance 45pF in sample mode. |
| REF (8–10) | Reference Input | Single-ended reference input (2.5V–5.1V); requires 47µF X7R ceramic decoupling at pin. |
| SEL0/SEL1 (11,12) | Down-Sampling Control | Binary-select inputs for digital filter DF = 4, 8, 16, or 32 - sets trade-off between speed and DR. |
| MCLK (13) | Master Clock Input | Rising edge initiates conversion; also powers up device - eliminates need for separate reset sequence. |
| SYNC (14) | Multi-Device Sync | Asynchronous pulse aligns digital filter phase across multiple LTC2512-24 devices for coherent sampling. |
| DRL (15) | Data Ready Indicator | Active-low pulse indicates new filtered output code is ready in SDOA register. |
| SDOA / SCKA (17,18) | Filtered Serial Interface | 24-bit 2's complement output (MSB-first) clocked by SCKA; compatible with standard SPI timing. |
| SDOB / SCKB (20,19) | No-Latency Serial Interface | 22-bit composite output (14-bit diff + 8-bit CM) clocked by SCKB; available every conversion cycle. |
| BUSY (21) | Conversion Status | High during conversion; low when result is latched - provides hardware-ready indication for DMA or interrupt handling. |
| OVDD (22) | Digital I/O Supply | 1.71V–5.25V logic supply; sets voltage thresholds for all digital pins (RDLx, SCKx, SDOx, SYNC, etc.). |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent output paths | Simultaneous 24-bit filtered and 22-bit no-latency outputs enable closed-loop control and high-fidelity recording in one IC. |
| Configurable flat-passband digital filter | Four pin-selectable down-sampling ratios (4–32) allow precise tailoring of bandwidth, noise floor, and output rate per application. |
| Wide common-mode input range (0V to VREF) | Eliminates need for input level-shifting circuitry when interfacing with sensors or amplifiers operating near rail. |
| Synchronization input (SYNC) | Enables deterministic phase alignment of digital filters across multiple ADCs - essential for multi-channel coherent sampling. |
| Relaxed analog anti-aliasing requirements | Digital filtering reduces aliasing susceptibility, permitting simpler, lower-order external RC anti-alias filters. |
Applications
| Seismology Data Acquisition | Energy Exploration Sensors |
|---|---|
Use Scenario: High-resolution digitization of low-amplitude geophone signals in borehole and surface arrays under extreme temperature and EMI conditions. IC Role / Device Role / Timing Role: Primary 24-bit ADC capturing microseismic events with ±1ppm INL and 117dB DR at 50ksps for spectral fidelity. Use Value: Enables detection of sub-micron ground motion with minimal post-processing, reducing false positives in reservoir monitoring. | Use Scenario: Downhole logging tools measuring resistivity, gamma ray, and acoustic impedance in oil/gas exploration rigs. IC Role / Device Role / Timing Role: Precision sensor interface ADC with wide common-mode range accepting signals from isolated front-end amplifiers. Use Value: Eliminates level-shifting circuitry and improves channel density in space-constrained tool string electronics. |
| Automated Test Equipment (ATE) | High-Accuracy Instrumentation |
Use Scenario: Calibration-grade source-measure units verifying DMMs, calibrators, and sensor simulators with traceable accuracy. IC Role / Device Role / Timing Role: Metrology engine providing 24-bit no-missing-codes performance and <1ppm INL over 0°C–70°C. Use Value: Reduces calibration drift and extends time-between-calibrations for Class I laboratory standards. | Use Scenario: Portable power quality analyzers measuring harmonic distortion, flicker, and transient events in grid-edge inverters. IC Role / Device Role / Timing Role: Dual-output ADC supplying real-time 14-bit differential data for control loops and 24-bit filtered data for compliance reporting. Use Value: Achieves IEC 61000-4-30 Class A compliance while maintaining sub-cycle response for fault detection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-resolution SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS127L01 | 24-bit delta-sigma ADC with 400ksps max output rate; fixed 128× oversampling; no dual-output mode. | Optimized for low-drift DC measurements; lacks no-latency output for real-time control. | Select when long-term stability and ultra-low drift (<0.1ppm/°C) outweigh need for zero-latency feedback. |
| AD7768-1 | 24-bit delta-sigma ADC with 256ksps output rate; integrated buffer; SPI interface only; no pin-strappable filter. | Includes on-chip programmable gain amplifier and reference; higher power (43mW). | Select when system integration (PGA + ref + ADC) reduces board area more than dual-output flexibility. |
Compared with ADS127L01 and AD7768-1, the LTC2512-24 uniquely combines true SAR architecture (no latency, no idle tones), pin-configurable digital filtering, and simultaneous high-precision + real-time outputs - making it optimal for hybrid measurement-and-control systems where both accuracy and responsiveness are mandatory.
Availability
LTC2512-24 is available at Aetrix Electronics and suitable for seismic monitoring, energy exploration instrumentation, and automated test equipment requiring stable component supply, long-lifecycle support, and guaranteed parametric performance across temperature.
Supply support for LTC2512-24 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, communications, automotive, and healthcare markets.
The LTC2512-24 belongs to ADI's precision data acquisition product line, designed specifically for applications demanding metrology-grade linearity, ultra-low noise, and flexible digital filtering - such as geophysical sensing, calibration infrastructure, and high-end test systems.
FAQ
What is the maximum sampling frequency of the LTC2512-24?
The LTC2512-24 supports a maximum sampling frequency of 1.6Msps. At this rate, the no-latency 22-bit output (SDOB) is fully available, while the 24-bit filtered output (SDOA) operates at up to 400ksps depending on the selected down-sampling factor. The device maintains guaranteed 24-bit no-missing-codes performance across its entire operating range, including at 1.6Msps acquisition.
How does the digital filter configuration affect the LTC2512-24's dynamic range and output data rate?
The LTC2512-24's digital filter down-sampling factor (DF) is set by SEL0/SEL1 pins and directly trades off output data rate against dynamic range: DF=4 yields 400ksps and 108dB DR; DF=8 gives 200ksps and 111dB; DF=16 gives 100ksps and 114dB; DF=32 gives 50ksps and 117dB. All configurations maintain the same 24-bit resolution and ±1ppm INL.
Can the LTC2512-24 operate with different reference voltages, and how does that impact LSB size?
Yes, the LTC2512-24 accepts reference voltages from 2.5V to 5.1V. LSB size scales linearly with VREF: at 5.0V reference, LSB = 596nV; at 2.5V, LSB = 298nV. This allows users to match input signal amplitude to full-scale range while preserving 24-bit resolution and maintaining >110dB DR across the supported VREF range.
What is the function of the SYNC pin on the LTC2512-24, and how is it used in multi-device systems?
The SYNC pin on the LTC2512-24 provides asynchronous phase alignment of the internal digital filter across multiple devices. A rising edge on SYNC resets the filter state, ensuring coherent sampling and synchronized output timing - critical for multi-channel systems like phased-array seismometers or synchronized ATE channels. No external clock distribution is required.
Does the LTC2512-24 require external anti-aliasing filters, and how does its digital filter relax those requirements?
The LTC2512-24's integrated digital lowpass filter significantly relaxes analog anti-aliasing requirements. With DF=32, its effective Nyquist bandwidth is ~25kHz, allowing use of simple first-order RC filters instead of steep 8th-order analog filters. This reduces component count, board area, and phase distortion - while still meeting stringent alias rejection specs due to the filter's flat passband and sharp roll-off.
DC2222A-C Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Packaging:
- Box
- Product Status:
- Active
- Number of A/D Converters:
- 1
- Number of Bits:
- 24
- Sampling Rate (Per Second):
- 1.6M
- Data Interface:
- SPI
- Input Range:
- ±VREF
- Power (Typ) @ Conditions:
- 30mW @ 1.6MSPS
- Utilized IC / Part:
- LTC2512-24
- Contents:
- Board(s)
DC2222A-C FAQ
1.How can I place an order for DC2222A-C through Aetrix?
Please submit a Request for Quotation (RFQ) for DC2222A-C on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DC2222A-C reliable?
The price and inventory of DC2222A-C are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DC2222A-C is usually 5 days.
3.What payment methods are accepted for DC2222A-C?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DC2222A-C transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DC2222A-C?
DC2222A-C orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DC2222A-C order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DC2222A-C?
For technical support, including DC2222A-C datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DC2222A-C requirements.
6.How does Aetrix verify that DC2222A-C is sourced from the original manufacturer or authorized distributors?
All DC2222A-C products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DC2222A-C meets industry standards.
7.What is the process for return or replacement of DC2222A-C?
All DC2222A-C units undergo pre-shipment inspection (PSI). If there is an issue with DC2222A-C, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DC2222A-C part is unused and in its original packaging.
Return procedure for DC2222A-C:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DC2222A-C Tags

-
1083
Adafruit Industries LLC

-
1085
Adafruit Industries LLC

-
ADS7038Q1EVM-PDK
Texas Instruments

-
ADS8688EVM-PDK
Texas Instruments

-
EVAL-AD7606C18FMCZ
Analog Devices Inc.

-
ADS1232REF
Texas Instruments

-
EVAL-AD4134FMCZ
Analog Devices Inc.

-
EVAL-AD7768FMCZ
Analog Devices Inc.

-
ADC128S102EVM
Texas Instruments

-
ADS124S08EVM
Texas Instruments

-
ADC6140EVM-PDK
Texas Instruments

-
ADS7066EVM-PDK
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

