My Inquiry
My Account
Analog Devices Inc. DC2290A-E
- Part No.:
- DC2290A-E
- Manufacturer:
- Analog Devices Inc.
- Package:
- Datasheet:
-
DC2290A-E.pdf
- Description:
- EVAL BOARD FOR LTC2385-18
- Quantity:
- Payment:
- Shipping:
Inventory:1,290
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2385-18 from Analog Devices (acquired Linear Technology) is an 18-bit, 5 Msps successive approximation register (SAR) analog-to-digital converter with serial LVDS interface, ±4.096 V differential input range, 95.7 dB SNR at 1 MHz, and no pipeline latency-designed for high-speed imaging, instrumentation, and closed-loop control systems requiring precise wide-dynamic-range digitization.
For engineers reviewing the LTC2385-18 datasheet, LTC2385-18 pinout, LTC2385-18 application, or LTC2385-18 equivalent, this page delivers verified technical context, real-world design meaning of key specs, validated pin functions, application-specific implementation guidance, and two confirmed alternative SAR ADCs with documented functional and packaging differences.
Technical Context
The LTC2385-18 employs a fully differential SAR architecture with internal 2.048 V reference and 2× gain reference buffer (4.096 V output), enabling direct interfacing to ±4.096 V inputs without external signal conditioning. Its no-latency operation ensures deterministic timing critical for real-time control loops.
It uses a serial LVDS interface supporting one-lane (18-bit/5 Msps) or two-lane (9-bit/5 Msps per lane) modes, reducing PCB routing complexity while maintaining signal integrity at high data rates. Conversion is triggered by LVDS or CMOS-compatible CNV+/- inputs, with acquisition time of tCYC – 67 ns and conversion time ≤101 ns.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 18-bit - guarantees no missing codes and 31.25 µV LSB step size with 4.096 V reference, enabling sub-µV-level measurement resolution in precision systems. |
| Sampling Rate | 5 Msps - supports Nyquist sampling up to 2.5 MHz input bandwidth, suitable for ultrasound, LIDAR, and high-speed data acquisition. |
| SNR | 95.7 dB (typ) at fIN = 1 MHz - corresponds to ~20.5 effective bits, minimizing quantization noise in dynamic signal capture. |
| INL | ±1.5 LSB (max) - ensures monotonicity and linearity error < 0.0036% FSR, critical for calibration-sensitive instrumentation. |
| Power Dissipation | 78 mW at 5 Msps - enables high-speed operation in thermally constrained embedded systems without active cooling. |
| Reference | Internal 2.048 V ±0.25% initial accuracy, ±20 ppm/°C max TC - eliminates need for external reference in cost-sensitive designs while maintaining stability over industrial temperature range. |
| Interface | LVDS serial output (one- or two-lane) - reduces I/O count vs parallel interfaces and improves noise immunity in mixed-signal PCB layouts. |
Pinout & Package
32-pin (5 mm × 5 mm) QFN package with exposed thermal pad (Pin 33 = GND). Requires soldering exposed pad to PCB ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Pins 1, 4, 10, 21, 26, 29) | Ground reference | Multiple dedicated ground pins minimize ground bounce and ensure stable reference for analog and digital sections. |
| IN+, IN– (Pins 2, 3) | Differential analog input | Accepts ±4.096 V differential swing with common-mode range centered at 2.048 V; requires matched 180° out-of-phase drive. |
| REFGND (Pins 5, 6) | Reference ground | Must be shorted together and connected directly to bypass capacitor and exposed pad to isolate reference return path from noisy digital currents. |
| REFBUF (Pins 7, 8) | Buffered reference output | Provides 4.096 V (2× internal 2.048 V ref); used as input common-mode voltage and full-scale reference for analog inputs. |
| REFIN (Pin 9) | Internal reference output / external reference input | Outputs 2.048 V internal reference; accepts external 2.008–2.088 V reference for improved accuracy or temperature stability. |
| VDD (Pins 11, 12) | 5 V analog supply | 4.75–5.25 V range powers core analog circuitry; dual pins reduce IR drop and improve PSRR. |
| PD (Pin 13) | Power-down enable | Active-low logic input (OVDD-referenced); reduces total current to 10 µW, enabling ultra-low-power standby in battery-operated systems. |
| CLK+/CLK– (Pins 23, 24) | LVDS clock input | Accepts 5 MHz LVDS clock; determines sampling rate and synchronizes serial data output timing. |
| CNV+/CNV– (Pins 27, 28) | LVDS conversion start | Rising edge on CNV+ initiates sample-and-hold hold mode and conversion; supports single-ended CMOS drive (CNV– tied to GND). |
| DA+/DA–, DB+/DB– (Pins 15–18) | LVDS serial data outputs | DA carries primary data stream; DB active only in two-lane mode - reduces EMI and simplifies FPGA/CPLD interface design. |
| DCO+/DCO– (Pins 19, 20) | LVDS data clock output | Echoes CLK input for source-synchronous data capture; eliminates need for separate clock routing to receiver. |
Key Features
| Feature | Design Value |
|---|---|
| No pipeline latency | Enables immediate use of conversion result in real-time feedback loops-no FIFO buffering or latency compensation required. |
| Guaranteed 18-bit no missing codes | Ensures monotonic transfer function across full temperature range, eliminating code ambiguities in precision metrology applications. |
| Internal 2.048 V reference with ±20 ppm/°C TC | Reduces BOM count and layout area versus external reference solutions while meeting industrial-grade drift requirements. |
| Two-lane LVDS output mode | Halves data rate per lane (2.5 Msps/lane), easing timing closure on FPGA receivers and lowering EMI compared to single-lane 5 Msps operation. |
| 78 mW power at full speed | Delivers high-resolution, high-speed performance within thermal budgets typical of compact industrial controllers and portable test equipment. |
Applications
| High-Speed Imaging | Communications Receiver |
|---|---|
Use Scenario: Digitizing analog video signals from scientific CCD/CMOS sensors operating at >2 MHz pixel clock rates. IC Role / Device Role / Timing Role: Primary SAR ADC capturing full-frame analog outputs with deterministic 200 ns conversion cycle time and zero latency. Use Value: 95.7 dB SNR preserves low-contrast detail in medical or astronomical imaging; LVDS interface minimizes crosstalk in dense sensor array PCBs. |
Use Scenario: Baseband sampling in wideband SDR transceivers requiring >100 dB SFDR for adjacent-channel rejection. IC Role / Device Role / Timing Role: High-linearity ADC front-end for IF/RF sampling, leveraging ±1.5 LSB INL and 101 dB SFDR at 1 MHz. Use Value: Internal 2.048 V reference eliminates external reference drift-induced EVM degradation; two-lane LVDS eases FPGA interface timing. |
| Industrial Control Loop | Automated Test Equipment |
Use Scenario: Real-time position/force feedback in servo drives where ADC output must close loop within 1 µs. IC Role / Device Role / Timing Role: Latency-free SAR ADC providing immediate digital representation of motor current/voltage for PID computation. Use Value: No pipeline delay eliminates phase lag in control response; 5 Msps throughput supports multi-axis synchronized sampling. |
Use Scenario: Precision DC parametric testing of ICs and passive components requiring <0.01% absolute accuracy. IC Role / Device Role / Timing Role: Metrology-grade digitizer in ATE mainframe, using internal reference and buffered outputs for traceable measurements. Use Value: ±1.5 LSB INL and guaranteed no missing codes ensure pass/fail decisions meet Class A calibration standards; REFIN/REFBUF flexibility supports external metrology references. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD7960BCPZ-RL7 | 18-bit, 5 Msps, SPI interface (not LVDS); requires external reference; 91.5 dB SNR (typ); 32-lead LFCSP package. | Lacks LVDS serialization - increases FPGA I/O count and routing complexity; lower SNR limits dynamic range in low-noise applications. | Choose when SPI interface compatibility or ADI ecosystem integration outweighs LVDS noise immunity and reduced pin count. |
| ADS8860IPWR | 16-bit, 1 Msps, SPI interface; internal reference; 86 dB SNR (typ); 16-pin TSSOP package. | Lower resolution and speed; no LVDS; smaller package - unsuitable for 5 Msps or 18-bit requirements but lower cost and power (2.5 mW). | Choose for cost-sensitive, lower-performance applications where 16-bit resolution and 1 Msps suffice, and board space is highly constrained. |
Compared with AD7960BCPZ-RL7 and ADS8860IPWR, the LTC2385-18 uniquely combines 18-bit resolution, 5 Msps throughput, LVDS serialization, and integrated reference in a single 32-pin QFN-making it optimal for high-density, high-fidelity data acquisition where timing determinism and noise immunity are non-negotiable.
Availability
LTC2385-18 is available at Aetrix Electronics and suitable for high-speed imaging, industrial control loops, and automated test equipment requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature grade availability.
Supply support for LTC2385-18 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2385-18 belongs to ADI's high-speed precision SAR ADC product line, engineered specifically for applications demanding both wide dynamic range and deterministic timing-such as real-time spectrum analysis, laser distance measurement, and closed-loop motion control.
FAQ
What is the maximum input frequency supported by the LTC2385-18?
The LTC2385-18 supports Nyquist sampling up to 2.5 MHz input frequency, with –3 dB input bandwidth specified at 200 MHz. Its 95.7 dB SNR at 1 MHz and 101 dB SFDR confirm usable dynamic range well into the MHz range, making it suitable for undersampling applications such as IF digitization in communications receivers.
Does the LTC2385-18 require an external reference?
No-the LTC2385-18 includes an internal 2.048 V reference with ±0.25% initial accuracy and ±20 ppm/°C max temperature coefficient. It also provides a 4.096 V buffered output (REFBUF) for analog input common-mode setting. An external reference can be applied to REFIN if higher accuracy or custom voltage is needed.
How does the two-lane LVDS mode affect timing and FPGA interface design for the LTC2385-18?
In two-lane LVDS mode (enabled via TWOLANES pin), the LTC2385-18 outputs 9 bits per lane at 2.5 Msps instead of 18 bits at 5 Msps on a single lane. This halves the data rate per differential pair, relaxing setup/hold timing margins on FPGA receivers and reducing EMI. DCO remains synchronized to CLK, preserving source-synchronous capture integrity.
What is the power consumption of the LTC2385-18 in power-down mode?
The LTC2385-18 draws only 10 µW in power-down mode when the PD pin is asserted low. This ultra-low standby power enables energy-efficient operation in battery-powered or duty-cycled systems such as portable diagnostic instruments or remote sensor nodes.
Can the LTC2385-18 be driven with a single-ended CNV signal?
Yes-the LTC2385-18 supports single-ended CNV operation: tie CNV– to GND and drive CNV+ with a 2.5 V CMOS signal. The rising edge on CNV+ initiates conversion. This simplifies timing generation in systems lacking LVDS clock sources while retaining full 5 Msps throughput capability.
DC2290A-E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Packaging:
- Box
- Product Status:
- Active
- Number of A/D Converters:
- 1
- Number of Bits:
- 18
- Sampling Rate (Per Second):
- 5M
- Data Interface:
- LVDS - Serial
- Input Range:
- -
- Power (Typ) @ Conditions:
- 78mW @ 5MSPS
- Utilized IC / Part:
- LTC2385-18
- Contents:
- Board(s)
DC2290A-E FAQ
1.How can I place an order for DC2290A-E through Aetrix?
Please submit a Request for Quotation (RFQ) for DC2290A-E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DC2290A-E reliable?
The price and inventory of DC2290A-E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DC2290A-E is usually 5 days.
3.What payment methods are accepted for DC2290A-E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DC2290A-E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DC2290A-E?
DC2290A-E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DC2290A-E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DC2290A-E?
For technical support, including DC2290A-E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DC2290A-E requirements.
6.How does Aetrix verify that DC2290A-E is sourced from the original manufacturer or authorized distributors?
All DC2290A-E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DC2290A-E meets industry standards.
7.What is the process for return or replacement of DC2290A-E?
All DC2290A-E units undergo pre-shipment inspection (PSI). If there is an issue with DC2290A-E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DC2290A-E part is unused and in its original packaging.
Return procedure for DC2290A-E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DC2290A-E Tags
-
1083
Adafruit Industries LLC
-
1085
Adafruit Industries LLC
-
ADS7038Q1EVM-PDK
Texas Instruments
-
ADS8688EVM-PDK
Texas Instruments
-
EVAL-AD7606C18FMCZ
Analog Devices Inc.
-
ADS1232REF
Texas Instruments
-
EVAL-AD4134FMCZ
Analog Devices Inc.
-
EVAL-AD7768FMCZ
Analog Devices Inc.
-
ADC128S102EVM
Texas Instruments
-
ADS124S08EVM
Texas Instruments
-
ADC6140EVM-PDK
Texas Instruments
-
ADS7066EVM-PDK
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
